CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
D
D
D
D
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
Contains Four Flip-Flops With Double-Rail
Outputs
Buffered Inputs
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA
Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
E OR M PACKAGE
(TOP VIEW)
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
description/ordering information
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION
TA
PDIP – E
–55°C to 125°C
SOIC – M
PACKAGE†
Tube
Tube
Tape and reel
ORDERABLE
PART NUMBER
CD74ACT175E
CD74ACT175M
CD74ACT175M96
TOP-SIDE
MARKING
CD74ACT175E
ACT175M
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
L
H
H
H
CLK
X
↑
↑
L
D
X
H
L
X
OUTPUTS
Q
L
H
L
Q0
Q
H
L
H
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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•
DALLAS, TEXAS 75265
1
CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
logic diagram (positive logic)
CLR
1
CLK
1D
9
4
1D
C1
R
2
1Q
1Q
3
To Three Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, I
IK
(V
I
< 0 V or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 V or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous output current, I
O
(V
O
> 0 V or V
O
< V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
VCC
VCC
–24
24
10
0
0
MAX
5.5
–55°C to
125°C
MIN
4.5
2
0.8
VCC
VCC
–24
24
10
0
0
MAX
5.5
–40°C to
85°C
MIN
4.5
2
0.8
VCC
VCC
–24
24
10
MAX
5.5
V
V
V
V
V
mA
mA
ns/V
UNIT
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
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CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
µA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50
µA
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
II
ICC
VI = VCC or GND
VI = VCC or GND,
VI = VCC – 2.1 V
IO = 0
VCC
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.5 V to 5.5 V
±0.1
8
2.4
10
±1
160
3
10
0.1
0.36
0.1
0.5
1.65
1.65
±1
80
2.8
10
µA
µA
mA
pF
TA = 25°C
MIN
4.4
3.94
MAX
–55°C to
125°C
MIN
4.4
3.7
3.85
3.85
0.1
0.44
V
MAX
–40°C to
85°C
MIN
4.4
3.8
V
MAX
UNIT
VOH
VI = VIH or VIL
VOL
VI = VIH or VIL
D
ICC‡
Ci
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
ACT INPUT LOAD TABLE
INPUT
Data
CLR
CLK
UNIT LOAD
0.58
0.67
0.92
Unit Load is
∆I
CC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted)
–55°C to
125°C
MIN
fclock
tw
tsu
th
trec
Clock frequency
Pulse duration
Setup time before CLK↑
Hold time, data after CLK↑
Recovery time, before CLK↑
CLR↑
CLR low
CLK high or low
Data
4
5
2
2
1
MAX
114
3.5
4.4
2
2
1
–40°C to
85°C
MIN
MAX
114
MHz
ns
ns
ns
ns
UNIT
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3
CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
–55°C to
125°C
MIN
114
CLK
CLR
Any Q
Any Q
2.9
2.9
3.3
3.3
11.5
11.5
13
13
MAX
–40°C to
85°C
MIN
114
3
3
3.3
3.3
10.5
10.5
11.8
11.8
MAX
MHz
ns
ns
UNIT
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TYP
55
UNIT
pF
4
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CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
PARAMETER MEASUREMENT INFORMATION
R1 = 500
Ω
S1
2
×
VCC
Open
GND
R2 = 500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
GND
From Output
Under Test
CL = 50 pF
(see Note A)
tw
3V
LOAD CIRCUIT
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
0V
tsu
Data
Input
1.5 V
10%
90%
tr
th
90%
3V
1.5 V
10% 0 V
tf
1.5 V
0V
CLR
Input
3V
1.5 V
0V
trec
3V
Reference
Input
CLK
1.5 V
0V
VOLTAGE WAVEFORMS
RECOVERY TIME
3V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
1.5 V
tPLH
1.5 V
0V
tPHL
90%
tr
90%
VOH
50% VCC
10%
VOL
tf
90%
tr
VOH
VOL
Output
Control
tPZL
3V
1.5 V
1.5 V
0V
tPLZ
20% VCC
tPZH
≈V
CC
20% VCC
VOL
tPHZ
80% VCC
VOH
80% VCC
≈0
V
In-Phase
Output
50%
10%
tPHL
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
