S E M I C O N D U C T O R
CD74FCT153T, CD74FCT253T,
CD74FCT2153T, CD74FCT2253T
High-Speed CMOS Dual 4-Input Multiplexer
Description
The CD74FCT153T, CD74FCT253T, CD74FCT2153T and
CD74FCT2253T are high-speed dual 4-input multiplexers.
The CD74FCT153T and CD74FCT2153T have TTL outputs,
while the CD74FCT253T and CD74FCT2253T have threes-
tate outputs. The output buffers are designed with a poweroff
disable allowing ‘live insertion’ of boards when used as back-
plane drivers.
The CD74FCT2153T and CD74FCT2253T devices have a
built-in 25Ω series resistor on all outputs to reduce noise due
to reflections, thus eliminating the need for an external termi-
nating resistor.
December 1996
Features
• Advanced 0.8 micron CMOS Technology
• These Devices are Pin Compatible with Bipolar
FAST™ Series at a Higher Speed and Lower Power
Consumption
• 25Ω Series Resistor On All Outputs (FCT2XXX Only)
• TTL Input and Output Levels
• Low Ground Bounce Outputs (25Ω Series Only)
• Extremely Low Static Power
• Hysteresis on All Inputs
Ordering Information
TEMP.
PKG.
o
C) PACKAGE
PART NUMBER
RANGE (
NO.
CD74FCT153TM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT153ATM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT153CTM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT153TNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT153ATNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT153CTNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT153TQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT153ATQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT153CTQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT253TM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT253ATM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT253CTM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT253TNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT253ATNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT253CTNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT253TQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT253ATQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT253CTQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2153TM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2153ATM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2153CTM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2153TNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2153ATNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2153CTNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2153TQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2153ATQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2153CTQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2253TM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2253ATM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2253CTM
-40 to 85
16 Ld SOIC M16.3-P
CD74FCT2253TNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2253ATNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2253CTNM
-40 to 85
16 Ld SOIC M16.15-P
CD74FCT2253TQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2253ATQM
-40 to 85
16 Ld QSOP M16.15A-P
CD74FCT2253CTQM
-40 to 85
16 Ld QSOP M16.15A-P
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
Pinout
CD74FCT153T, CD74FCT253T,
CD74FCT2153T, CD74FCT2253T
(QSOP, SOIC)
TOP VIEW
E
A
1
S
1
2
I
3A
3
I
2A
4
I
1A
5
I
0A
6
O
A
7
GND 8
16 V
CC
15 E
B
14 S
0
13 I
3B
12 I
2B
11 I
1B
10 I
0B
9 O
B
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
1
Copyright
©
Harris Corporation 1996
File Number
4161.2
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
Functional Block Diagram
E
B
E
A
S
1
S
0
I
0A
I
1A
I
2A
I
3A
I
0B
I
1B
I
2B
I
3B
THREE-STATE ENABLE
ON CD74FCT253T ONLY
O
A
O
B
TRUTH TABLE
(NOTE 1)
OUTPUTS
INPUTS
E
A
H
X
L
L
L
L
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance
E
B
X
H
L
L
L
L
S
1
X
X
L
L
H
H
S
0
X
X
L
H
L
H
CD74FCT153, CD74FCT2153
O
A
L
X
I
0A
I
1A
I
2A
I
3A
O
B
X
L
I
0B
I
1B
I
2B
I
3B
CD74FCT253, CD74FCT2253
O
A
Z
X
I
0A
I
1A
I
2A
I
3A
O
B
X
Z
I
0B
I
1B
I
2B
I
3B
Pin Description
PIN NAME
I
0A
-I
3A
, I
0B
-I
3B
S
0
, S
1
E
A
, E
B
O
A
, O
B
GND
V
CC
Data Inputs
Select Inputs
Enable Input
Data Outputs
Ground
Power
DESCRIPTION
2
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
Absolute Maximum Ratings
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(
o
C/W)
16 Lead SOIC (150 mil) Package . . . . . . . . . . . . . .
110
16 Lead SOIC (300 mil) Package . . . . . . . . . . . . . .
97
16 Lead QSOP Package . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage to Ground Potential
Inputs and V
CC
Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS
SYMBOL
(NOTE 3)
TEST CONDITIONS
MIN
(NOTE 4)
TYP
MAX
UNITS
DC ELECTRICAL SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±
5%
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
High Impedance
Output Current
Clamp Diode Voltage
Short Circuit Current
Power Down Disable
Input Hysteresis
V
OH
V
OL
V
OL
V
IH
V
IL
I
IH
I
IL
I
OZH
,
I
OZL
V
IK
I
OS
I
OFF
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= Min, V
IN
= V
IH
or V
IL
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max
V
CC
= Max
V
CC
= Max
V
CC
= Min, I
IN
= -18mA
V
CC
= Max (Note 5),
V
OUT
= GND
V
CC
= GND, V
OUT
= 4.5V
V
IN
= V
CC
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
-
-60
-
-
-0.7
-120
-
200
I
OH
= -15.0mA
I
OL
= 48mA
I
OL
= 12mA
(25Ω series)
2.4
-
-
2.0
-
-
-
3.0
0.3
0.3
-
-
-
-
-
0.50
0.50
-
0.8
1
-1
1
-1
-1.2
-
100
-
V
V
V
V
V
µA
µA
µA
µA
V
mA
µA
mV
V
H
o
C, f = 1MHz
CAPACITANCE
T
A
= 25
Input Capacitance
(Note 6)
Output Capacitance
(Note 6)
C
IN
C
OUT
V
IN
= 0V
V
OUT
= 0V
-
-
6
8
10
12
pF
pF
POWER SUPPLY SPECIFICATIONS
Quiescent Power
Supply Current
Supply Current per
Input at TTL HIGH
Supply Current per
Input per MHz
(Note 8)
Total Power Supply
Current (Note 10)
I
CC
∆I
CC
I
CCD
V
CC
= Max
V
CC
= Max
V
CC
= Max, Outputs Open
Other Inputs at GND
One Bit Toggling
50% Duty Cycle
V
CC
= Max, Outputs Open
f
I
= 10MHz, 50% Duty Cycle
Other Inputs at GND
One Bit Toggling
V
IN
= GND or V
CC
V
IN
= 3.4V
(Note 7)
V
IN
= V
CC
V
IN
= GND
-
-
-
0.1
0.5
0.15
500
2.0
0.25
µA
mA
mA/
MHz
I
C
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
-
-
3.2
3.5
6.5
(Note 9)
7.5
(Note 9)
mA
mA
3
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
Switching Specifications Over Operating Range
(NOTE 11)
TEST
CONDITIONS
C
L
= 50pF
R
L
= 500Ω
T
(NOTE 12)
MIN
1.5
1.5
1.5
MAX
9.0
7.0
7.0
AT
(NOTE 12)
MIN
1.5
1.5
1.5
MAX
6.6
5.2
5.2
CT
(NOTE 12)
MIN
1.5
1.5
1.5
MAX
5.6
4.5
4.8
UNIT
ns
ns
ns
PARAMETER
Propagation Delay
Sn to O
Propagation Delay
In to O
Propagation Delay
E to O
Propagation Delay
Sn to O
Propagation Delay
In to O
Output Enable Time
E to O
Output Enable Time
E to O (Note 13)
NOTES:
SYMBOL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PZH
,
t
PZL
t
PHZ
,
t
PLZ
CD74FCT153T, CD74FCT2153T
CD74FCT253T, CD74FCT2253T
C
L
= 50pF
R
L
= 500Ω
1.5
1.5
1.5
1.5
9.0
7.0
9.0
7.0
1.5
1.5
1.5
1.5
6.6
5.2
6.0
6.0
1.5
1.5
1.5
1.5
5.6
4.5
5.0
5.0
ns
ns
ns
ns
3. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
4. Typical values are at V
CC
= 5.0V, 25
o
C ambient and maximum loading.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
6. This parameter is determined by device characterization but is not production tested.
7. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
8. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
9. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
10. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (Vin = 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
11. See test circuit and wave forms.
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. This parameter is guaranteed but not production tested.
4
CD74FCT153T, CD74FCT253T, CD74FCT2153T, CD74FCT2253T
Test Circuits and Waveforms
V
CC
7.0V
500Ω
PULSE
GENERATOR
V
IN
DUT
50pF
C
L
V
OUT
SWITCH POSITION
TEST
t
PLZ
, t
PZL
t
PHZ
, t
PZH
, t
PLH
, t
PHL
SWITCH
Closed
Open
R
T
500Ω
DEFINITIONS:
C
L
= Load capacitance, includes jig and probe capacitance.
R
T
= Termination resistance, should be equal to Z
OUT
of the
Pulse Generator.
NOTE:
14. Pulse Generator for All Pulses: Rate
≤
1.0MHz; Z
OUT
≤
50Ω;
t
f
, t
r
≤
2.5ns.
FIGURE 1. TEST CIRCUIT
ENABLE
CONTROL INPUT
t
PZL
3.5V
OUTPUT
NORMALLY LOW
SWITCH
CLOSED
t
PZH
OUTPUT
NORMALLY HIGH
SWITCH
OPEN
1.5V
0V
1.5V
DISABLE
3V
1.5V
0V
t
PLZ
3.5V
0.3V
t
PHZ
0.3V
OUTPUT
V
OL
V
OH
0V
OPPOSITE PHASE
INPUT TRANSITION
t
PLH
t
PHL
3V
1.5V
0V
SAME PHASE
INPUT TRANSITION
t
PLH
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
FIGURE 2. ENABLE AND DISABLE TIMING
FIGURE 3. PROPAGATION DELAY
5
