CS61577
T1/E1 Line Interface
Features
General Description
The CS61577 is a drop-in replacement for the
CS61574, and combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61577 supports processor-based or stand-
alone operation and interfaces with industry standard
T1 and E1 framers.
The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The receiver
includes a jitter attenuator optimized for minimum delay
in switching and transmission applications. The trans-
mitter provides internal pulse shaping to insure
compliance with T1 and E1 pulse template specifica-
tions.
•
Provides Analog Transmission Line
the Following Enhancements:
-
Lower Power Consumption
-
Interface for T1 and E1 Applications
•
Drop-in Replacement for CS61574 with
Transmitter Short-Circuit
Current Limiting
Greater Transmitter Immunity
to Line Reflections
Software Selection Between 75
Ω
and
120
Ω
E1 Output Options
Internally Controlled E1 Pulse Width
B8ZS/HDB3/AMI Encoder/Decoder
( ) = Pin Function in
Host Mode
[ ] = Pin Function in
Extended Hardware Mode
2
TCLK
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
RPOS
[RDATA]
RNEG
[BPV]
3
R
E
M
O
T
E
L
O
O
P
B
A
C
K
26
-
Applications
-
•
•
Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect
Building Channel Service Units
-
-
ORDERING INFORMATION
CS61577-IP1
28 Pin Plastic DIP
CS61577-IL1
28 Pin Plastic PLCC
MODE
5
(CLKE) (INT) (SDI) (SDO)
TAOS LEN0 LEN1 LEN2
28
23
24
25
TGND
TV+
4
L
O
C
A
L
L
O
O
P
B
A
C
K
1
15
14
LINE DRIVER
13
16
CONTROL
PULSE
SHAPER
LINE RECEIVER
TTIP
TRING
8
7
AMI,
B8ZS,
HDB3,
CODER
19
20
17
JITTER
ATTENUATOR
CLOCK &
DATA
RECOVERY
SIGNAL
QUALITY
MONITOR
RTIP
RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]
6
DRIVER
MONITOR
22
RGND
18
11
9
10
27
LLOOP
(SCLK)
12
LOS
21
RV+
RLOOP XTALIN XTALOUT ACLKI
(CS)
Preliminary Product Information
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581
This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Copyright
©
Crystal Semiconductor Corporation 1996
(All Rights Reserved)
MAY ’96
DS155PP2
1
CS61577
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Units
DC Supply
RV+
-
6.0
V
TV+
-
(RV+) + 0.3
V
Input Voltage, Any Pin
(Note 1)
V
in
RGND-0.3
(RV+) + 0.3
V
Input Current, Any Pin
(Note 2)
I
in
-10
10
mA
Ambient Operating Temperature
T
A
-40
85
°C
Storage Temperature
T
stg
-65
150
°C
WARNING:Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.
Parameter
(referenced to RGND=TGND=0V)
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
DC Supply
(Note 3) RV+, TV+
4.75
5.0
5.25
Ambient Operating Temperature
T
A
-40
25
85
-
400
500
Power Consumption
(Notes 4,5)
P
C
Power Consumption
(Notes 4,6)
P
C
-
230
-
Notes: 3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF
capacitive load.
5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line length at 5.0V.
Parameter
Units
V
°C
mW
mW
load.
DIGITAL CHARACTERISTICS
Parameter
(TA = -40°C to 85°C; TV+, RV+ = 5.0V
±5%;
GND = 0V)
Symbol
Min
Typ
Max
Units
V
V
V
V
µA
V
V
V
2.0
-
-
High-Level Input Voltage
(Notes 7, 8)
V
IH
PINS 1-4, 17, 18, 23-28
Low-Level Input Voltage
(Notes 7, 8)
V
IL
-
-
0.8
PINS 1-4, 17, 18, 23-28
High-Level Output Voltage
(Notes 7, 8, 9)
V
OH
4.0
-
-
IOUT = -40
µA
PINS 6-8, 11, 12, 25
-
-
0.4
Low-Level Output Voltage
(Notes 7, 8, 9)
V
OL
IOUT = 1.6 mA
PINS 6-8, 11, 12, 23, 25
Input Leakage Current (Except Pin 5)
-
-
±10
Low-Level Input Voltage, PIN 5
V
IL
-
-
0.2
High-Level Input Voltage, PIN 5
V
IH
(RV+) - 0.2
-
-
Mid-Level Input Voltage, PIN 5
(Note 10)
V
IM
2.3
-
2.7
Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is
an open drain output and pin 25 is a tristate output.
8. This specification guarantees TTL compatibility (V
OH
= 2.4V @ I
OUT
= -40µA).
9. Output drivers will drive CMOS logic levels into a CMOS load.
10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
2
DS155PP2
CS61577
ANALOG SPECIFICATIONS
Parameter
(TA = -40°C to 85°C; TV+, RV+ = 5.0V
±5%;
GND = 0V)
Min
Typ
Max
Units
Transmitter
AMI Output Pulse Amplitudes
(Note 11)
2.14
2.37
2.6
V
E1, 75
Ω
(Note 12)
2.7
3.0
3.3
V
E1, 120
Ω
(Note 13)
2.7
3.0
3.3
V
T1, (FCC Part 68)
(Note 14)
2.4
3.0
3.6
V
T1, DSX-1
(Note 15)
Load Presented To Transmitter Output
(Note 11)
-
25
-
Ω
Jitter Added During Remote Loopback
(Note 16)
10Hz - 8kHz
-
0.005
-
UI
8kHz - 40kHz
-
0.008
-
UI
-
0.010
-
UI
10Hz - 40kHz
Broad Band
-
0.015
-
UI
Power in 2kHz band about 772kHz
(Notes 11, 17)
12.6
15
17.9
dBm
Power in 2kHz band about 1.544MHz
(Notes 11, 17)
-29
-38
-
dB
(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance
(Notes 11, 17)
-
0.2
0.5
dB
Transmitter Output Impedance
(Notes 17, 18)
-
-
10
Ω
Transmitter Short Circuit Current
(Notes 11, 19)
-
-
50
mA RMS
Notes: 11. Using a 0.47
µF
capacitor in series with the primary of a transformer recommended
in the Applications Section.
12. Pulse amplitude measured at the output of the transformer across a 75
Ω
load for line length
settings LEN2/1/0 = 0/0/1 and 0/0/0. For LEN2/1/0 = 0/0/0 only, a 4.4
Ω
resistor is required
in series with the transformer primary.
13. Pulse amplitude measured at the output of the transformer across a 120
Ω
load for line length
setting LEN2/1/0 = 0/0/0.
14. Pulse amplitude measured at the output of the transformer across a 100
Ω
load for line length
setting LEN2/1/0 = 0/1/0.
15. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from
LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1.
16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
17. Not production tested. Parameters guaranteed by design and characterization.
18. Measured between the TTIP and TRING pins at 772 kHz during marks and spaces.
19. Measured broadband through a 0.5
Ω
resistor across the secondary of the transmitter transformer
during the transmission of an all ones data pattern with LEN2/1/0 = 0/0/0 or 0/0/1.
DS155PP2
3
CS61577
ANALOG SPECIFICATIONS
Parameter
(TA = -40°C to 85°C; TV+, RV+ = 5.0V
±5%;
GND = 0V)
Min
-
-13.6
500
-
20)
21)
22)
23)
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
60
53
45
160
Typ
50k
-
-
0.30
65
65
50
175
Max
-
-
-
-
70
77
55
190
Units
Ω
dB
mV
V
% of peak
% of peak
% of peak
bits
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
Loss of Signal Threshold
Data Decision Threshold
T1, DSX-1
(Note
T1, DSX-1
(Note
T1, (FCC Part 68) and E1 (Note
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance
(Note
10kHz - 100kHz
2kHz
10Hz and below
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Notes 17, 24)
-
6
-
Hz
Attenuation at 10kHz Jitter Frequency
(Notes 17, 24)
-
50
-
dB
Attenuator Input Jitter Tolerance (Before Onset
12
23
-
UI
of FIFO Overflow or Underflow Protection)
(Notes 17, 24)
Notes: 20. For input amplitude of 1.2 V
pk
to 4.14 V
pk
.
21. For input amplitude of 0.5 V
pk
to 1.2 V
pk
and from 4.14 V
pk
to RV+.
22. For input amplitude of 1.05 V
pk
to 3.3 V
pk
.
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
4
DS155PP2
CS61577
T1 SWITCHING CHARACTERISTICS
Parameter
(TA = -40°C to 85°C; TV+, RV+ = 5.0V
±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Symbol
Min
Typ
Max
-
-
-
55
85
85
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
6.176000
Crystal Frequency
(Note 25)
f
c
TCLK Frequency
f
tclk
-
1.544
ACLKI Frequency
(Note 26)
f
aclki
-
1.544
RCLK Duty Cycle
(Note 27) t
pwh1
/t
pw1
45
50
Rise Time, All Digital Outputs
(Note 28)
t
r
-
-
Fall Time, All Digital Outputs
(Note 28)
t
f
-
-
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
t
su2
25
-
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
t
h2
25
-
RPOS/RNEG Valid Before RCLK Falling
(Note 29)
t
su1
150
274
RDATA Valid Before RCLK Falling
(Note 30)
t
su1
150
274
RPOS/RNEG Valid Before RCLK Rising
(Note 31)
t
su1
150
274
RPOS/RNEG Valid After RCLK Falling
(Note 29)
t
h1
150
274
RDATA Valid After RCLK Falling
(Note 30)
t
h1
150
274
RPOS/RNEG Valid After RCLK Rising
(Note 31)
t
h1
150
274
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. ACLKI provided by an external source or TCLK.
27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
E1 SWITCHING CHARACTERISTICS
Parameter
(TA = -40°C to 85°C; TV+, RV+ = 5.0V
±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Symbol
f
c
f
tclk
t
pwh2
/t
pw2
f
aclki
t
pwh1
/t
pw1
t
r
t
f
t
su2
t
h2
t
su1
t
su1
t
su1
t
h1
t
h1
t
h1
Min
-
-
40
-
45
-
-
25
25
100
100
100
100
100
100
Typ
8.192000
2.048
50
2.048
50
-
-
-
-
194
194
194
194
194
194
Max
-
-
60
-
55
85
85
-
-
-
-
-
-
-
-
Units
MHz
MHz
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
Crystal Frequency
(Note
TCLK Frequency
TCLK Duty Cycle for LEN2/1/0 = 0/0/0
(Note
ACLKI Frequency
(Note
RCLK Duty Cycle
(Note
Rise Time, All Digital Outputs
(Note
Fall Time, All Digital Outputs
(Note
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note
RDATA Valid Before RCLK Falling
(Note
RPOS/RNEG Valid Before RCLK Rising
(Note
RPOS/RNEG Valid After RCLK Falling
(Note
RDATA Valid After RCLK Falling
(Note
RPOS/RNEG Valid After RCLK Rising
(Note
DS155PP2
25)
32)
26)
27)
28)
28)
29)
30)
31)
29)
30)
31)
