CH5001A
CHRONTEL
CMOS Color Digital Video Camera
Features
• 352 x 288 active pixel array with color filters, 1/3 inch
lens format
¥
• Programmable formats CIF 352x288, QCIF 176x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit or 16-bit)
• Multidimensional automatic shutter control
• Below 5 LUX sensitivity
• Programmable I
2
C Serial bus control:
- Frame rate: 30fps-1fps in eight steps
- Gamma correction
- Shutter speed
- Analog gain
- 16 backlight compensation zones
- Black clamp level
- White balance adjustment
- Power down modes
Description
The CH5001 is a single chip active pixel CMOS color
video camera with digital video output in several formats.
Using sophisticated noise correction circuitry to minimize
fixed pattern noise and dark current effects, the CH5001
provides a supurb quality picture in a low cost device.
The CH5001 uses a proprietary autoshutter algorithm to
dynamically control the shutter time, analog gain, and
black clamp level, providing optimum picture and contrast
under all lighting conditions. The CH5001 also
incorporates extensive on-chip programmable digital
signal processing to maximize the usefulness of the device
in processor driven applications. This includes 16
programmable zones for backlight compensation,
allowing the user to adjust the image to their unique
lighting environment.
Additionally, at power-up the backlight compensation
zone, power-up condition, and direct A/D output modes
are selectable without IIC control by using the PUD pins.
Requiring a minimum of parts for operation, the CH5001
provides a low cost camera for the next generation video
conferencing, videophone, and surveillance products.
3
• Stand-alone 25fps PAL operation with all automatic
features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation
¥
Patent number x,xxx,xxx patents pending
Photocell
Array
R
O
W
T
I
M
I
N
G
352
Columns
Shutter
Control
I
2
C
BUS
SD
SC
AS
B
G
G
R
288
Rows
Color
Control
Row Decode
Timing
&
Mode
Control
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
MONO
TOUT/TOUTB
OVR
A/D
Gain
Black
Clamp
Matrix
Multiply
Gamma
Correct
RGB
to
YCrCB
Filter
Output
Format
Y[7:0]
C[7:0] PUD[6:0]
CRS
Figure 1: Block Diagram
201-0000-032 Rev 3.0, 6/2/99
1
CHRONTEL
CH5001A
RESET*
AS
MONO
CMB2
AVDD
TOUTB
DVDD
SC
SD
DGND
TOUT
AGND
51
50
49
48
2
1
52
47
46
45
44
43
42
41
40
39
38
37
36
35
34
DGND
VS*
HS*
DVDD
OVR
HREF
Y0
Y1
Y2
Y3
Y4
Y5
Y6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
7
6
5
4
3
VRS
AVDD
ARF
ARF2
AGND
CRF
VREF
AVDD
XI/FIN
XO
AGND
DGND
PDP*
DVDD
1mm
Image Array
30
31
C5, PUD5*
C6, PUD6
23
24
C2, PUD2*
27
C3, PUD3*
28
32
C7
C0, PUD0*
25
C1, PUD1*
26
DGND
C4, PUD4*
29
DVDD
CLKOUT
.600 in Sq
Figure 2: 52 Contact Ceramic LCC (Top View)
2
CRS
Y7
33
201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
CH5001A
60 um
1301 um
Image
Array
3670.3 um
Package
Centerline
CMOS Die
Package
Centerline
4906.7 um
Figure 3: CH5001 Array Image Offset
201-0000-032 Rev 3.0, 6/2/99
3
CHRONTEL
Table 1. Pin Descriptions
Pin
21-14
7, 11, 22, 34
4, 8, 24, 36
CH5001A
Type
Out
Power
Power
Symbol
Y[7:0]
DVDD
DGND
Description
Video Output
Provides the luminance data of the digital video output.
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH5001.
Digital Ground
Provides the ground reference for the digital section of CH5001. These
pins MUST be connected to the system ground.
Video Output
Chrominance data of the digital video output are provided by these
pins.
Cr Select
CRS specifies the CrCb data sequence. CRS is an alternating signal.
CRS=1 indicates that C[7:0] carry the Cr data. CRS=0 indicates C[7:0]
carry the Cb data.
Video Pixel Clock Output
This pin outputs a buffered clock signal which can be used to latch data
output by pins Y[7:0] and C[7:0].
Vertical Sync Output (active low)
Outputs a vertical sync pulse.
Horizontal Sync Output (active low)
Outputs a horizontal sync pulse.
Over Range
This pin is high when the A/D converter input is beyond the full scale
range of the A/D.
Horizontal Reference
Active video timing signal. This output is high when active data is being
output from the device, and low otherwise.
Serial Clock
IIC clock input pin.
Serial Data
IIC data input/output pin.
Chip Address Select (internal pullup)
This pin selects the IIC address for the device.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
Chip Reset (active low, internal pullup)
Puts all registers into power-on default states. The state at pin SD must
be HIGH during reset for proper initialization.
Crystal Output
A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached
between XO and XI/FIN.
Crystal Input or External input
A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached
between XO and XI/FIN. An external CMOS compatible clock can be
connected to XI/FIN as an alternative.
32-25
Out
C[7:0]
33
Out
CRS
23
Out
CLKOUT
9
10
12
Out
Out
Out
VS*
HS*
OVR
13
Out
HREF
6
5
2
In
In/Out
In
SC
SD
AS
3
In
RESET*
38
In/Out
XO
39
In
XI/FIN
4
201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
Table 1. Pin Descriptions
Pin
40, 46, 51
41
CH5001A
Symbol
AVDD
VREF
Type
Power
Out
Description
Analog Supply Voltage
Supplies the 5V power to the analog section of the CH5001.
Voltage Reference
VREF provides a 1.235V reference. A 0.01
µ
F decoupling capacitor
should be connected between VREF and AGND.
37, 43, 48
Power
AGND
Analog Ground
These pins provide the ground reference for the analog section of
CH5001. Pins
must
be connected to the system ground to prevent
latchup.
Column Filter
CRF provides a 2.5 V reference. A
0.1µF
decoupling capacitor should
be connected between CRF and AGND.
Test Mode I/O Pins
For test purposes only. Should be NC.
Array Filters
A 0.1uF decoupling capacitors should be connected between each of
the pins and AGND.
Array Bias Filter
VRS provides a 2.1V reference. A
0.1µF
decoupling capacitor should
be connected between VRS and AGND.
Monochrome (active high, internal pulldown)
Digital pin to select Color / Monochrome operation.
1= Monochrome 0=Color
Power Down Pin (active low, internal pullup)
0 = power down
Bias Filter
A 0.1
µ
F decoupling capacitor should be connected between CMB2 and
AGND.
Power Up Detect (internal pull-up)
These pins are shared with the C[6:0] chrominance output function. At
power-up they are inputs controlling the default value of IIC register bits
M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low.
NOTE: PUD[5:0]* are logically inverted
42
Out
CRF
49, 50
44, 45
In/Out
Out
TOUT, TOUTB
ARF2, ARF
47
Out
VRS
1
In
MONO
35
52
In
Out
PDP*
CMB2
31-25
In
PUD[5:0]*
PUD[6]
201-0000-032 Rev 3.0, 6/2/99
5
嵌入式系统
