PRODUCT BRIEF
CHL8112A/B
DIGITAL MULTI-PHASE BUCK CONTROLLER
PRELIMINARY
The I2C/PMBus interface can communicate with up to 16
CHL8112A/B based VR loops. Device configuration and
fault parameters are easily defined using the CHiL Intuitive
Power Designer (IPD) GUI and stored in on-chip NVM.
The CHL8112A/B provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal.
The CHL8112A/B also includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its “set-and-forget” methodology.
ISEN1
ISEN2
ISEN3
ISEN4
ISEN5
31
30
29
28
27
RCSP_L2
RCSM_L2
VCC
VSEN_L2
VRTN_L2
PWM5
PWM4
PWM3
PWM2
PWM1
26
25
24
23
22
21
15
16
17
18
19
20
FEATURES
5-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
AMD® SVI/G34 & Memory MPoL modes
Dual OCP support for I-spike enhanced AMD CPUs
SMB_Alert Pin for Servers
PMBus Address pin or Variable Gate Drive (CHL8112A)
2nd Temperature Sense (CHL8112B)
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per phase
CHiL Efficiency Shaping Features including Variable
Gate Drive (CHL8112A only), Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads and
Active Diode Emulation for Very Light Loads
CHiL Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Designed for use with coupled inductors
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both loops
Non-Volatile Memory (NVM) for custom configuration
Compatible with CHiL ATL and 3.3V tri-state Drivers
+3.3V supply voltage; 0ºC to 85ºC ambient operation
Pb-Free, RoHS, 6x6 40 pin QFN package
IRTN1
IRTN2
IRTN3
IRTN4
40
RCSP
RCSM
VCC
VSEN
VRTN
RRES
TSEN
V18A
VR_READY
1
/
PWRGD
2
VR_READY_L2
1
/ PWROK
2
1
2
3
4
5
6
7
8
9
10
39
38
37
36
35
34
33
32
CHL8112A/B
40 Pin 6x6 QFN
Top View
Notes
1
Pin definition in MPoL mode
2
Pin definition in AMD mode
41
GND
DESCRIPTION
The CHL8112A/B are dual-loop digital multi-phase buck
controllers that drive up to 5 phases. The CHL8112A/B is
fully AMD® SVI compliant on both loops and provides a Vtt
tracking function for DDR memory.
NVM storage saves pins and enables a small package size.
The CHL8112A/B includes the CHiL Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. CHiL Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. CHiL Dynamic Phase Control
adds/drops active phases based upon load current. The
CHL8112A/B can be configured to enter 1-phase operation
and active diode emulation mode automatically or by
command.
CHiL’s unique Adaptive Transient Algorithm (ATA), based
on proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors. In addition, a coupled inductor mode,
with phases added/dropped in pairs, enables further
improvement in transient response and form factor.
11
12
13
14
VR_HOT#
1
/
VRHOT_ICRIT#
2
SMB_DIO
VINSEN
IRTN5
SMB_CLK
Figure 1. CHL8112A & CHL8112B Packages
APPLICATIONS
AMD® SVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
Trademarks and registered trademarks are the property of the respective
owners.
PB0012 Rev. 0.04, August 25, 2010
Page 1 of 2
One Highwood Drive, Tewksbury, MA 01876
Tel: +1(978)-640-0011
www.chilsemi.com
© 2010 CHiL Semiconductor Corp. All rights reserved
VAR_GATE_PM_ADDR (CHL8112A)
TSEN2 (CHL8112B)
NC
1
/ VFIXEN
2
NC
1
/ SVC
2
NC
1
/ SVD
2
ENABLE
SMB_ALERT#
CHL8112A/B
PRODUCT BRIEF
DIGITAL MULTI-PHASE BUCK CONTROLLER
TYPICAL APPLICATIONS BLOCK DIAGRAMS
12V
1
R
series
R
Th
R
series
RCS
CCS
V
RCSP
PWM1
RCSM
VCC
21
39
ISEN1
40
IRTN1
V_VGD
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
V_CPU_L1
L
O
A
D
2
3
28
+3.3V
12V
V
V
4
VSEN
5 VRTN
6 RRES
7
R
Th2
V_VGD
PWM 2 22
37
ISEN2
38
IRTN2
12V
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
TSEN
V
V
8 V18A
CHL8112A
PWM3
23
35
ISEN3
V_VGD
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
R
VIN_1
11 VINSEN
V_VGD
PWM4
17
NC
1
/VFIXEN
2
18
NC
1
/SVD
2
19
NC
1
/SVC
2
15 VR_HOT#
1
/
VRHOT_ICRIT#
2
16
EN
24
33
34
V
V
+12V
VR_RDY_L1
1
/PWRGD
2
IRTN3 36
10
VR_RDY_L2
1
/PWROK
2
9
12V
V
R
VIN_2
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
CPU
Serial
Bus
ISEN4
IRTN4
V
V
V
From
System
+3.3V
12V
V
V
V_VGD
17
SMB_ALERT#
18
SMB_DIO
19
SMB_CLK
30 RCSP_L2
PWM5
ISEN5
IRTN5
25
31
32
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
V_CPU_L2
L
O
A
D
SMBus
V
V
V
R
series
R
Th
R
series
RCS
CCS
29
27
26
12V
RCSM_L2
VSEN_L2
VRTN_L2
VAR_GATE_ 20
PM_ADDR
V
V
Boot CHL8510
HiGate
Vcc
HVCC
Switch
LVCC
PWM
LoGate
GND
V_VGD
Optional Variable
Gate Drive Circuit
Notes
1
Pin definition in MPoL mode
2
Pin definition in AMD mode
GND
ORDERING INFORMATION
CHL8112
-
T: Tape & Reel
Package type
R : QFN
Operating Temperature
C: Commercial Standard
Range
R : QFN
xx: Configuration file
Part
A: CHL8112A
B: CHL8112B
Package
QFN
QFN
QFN
QFN
Notes
Tape & Reel Qty
3000
3000
3000
3000
Part Number
1
CHL8112A-00CRT
2
CHL8112A-xxCRT
1
CHL8112B-00CRT
2
CHL8112B-xxCRT
1. For unprogrammed/default parts, use configuration
file 00. Unprogrammed parts will not start up until
programmed in order to insure a safe power up.
2. -xx indicates a customer specific configuration file
Page 2 of 2
PB0012
Rev. 0.04, August 25, 2010
