ply, linear power amplifier module intended for use in cellular
handsets and wireless local loop subscriber units. The highly
integrated amplifier meets the requirements of CDMA and
CDMA2K 1X systems. It is a member of Celeritek’s new
TrueTriangle™
family of 3V power amplifier modules.
The CHP0230-PM is packaged in a low-cost, space
efficient, 6mm square, matched module that provides excellent
824 to 849 MHz
28.5 dBm, Cellular
InGaP HBT Amplifier Module
Functional Block Diagram
Vcc
1
RF IN
2
Vref
3
BIAS
Ground connection is
on backside
6
Vcc
5
RF OUT
4
N/C
electrical stability and low thermal resistance. The module
operates from a fixed positive voltage and requires no external
matching which significantly reduces space, cost and enhances
ease of use.
The 6x6 mm package is self contained, incorporating
50 ohm input and output matching networks optimized for
output power, linearity and efficiency.
Celeritek’s InGaP HBT technology offers a thermally
robust and reliable PAM (power amplifier module) solution.
Absolute Maximum Ratings
Parameter
Rating
Parameter
Rating
Parameter
Rating
Collector Voltage (+Vcc)
Collector Current (Icc)
RF Input Power
* RF Off.
+6.0 V*
1.2 A
7 dBm
Reference Voltage (Vref)
Power Dissipation
+3.1 V
5W
Operating Temperature
Storage Temperature
Soldering Temperature
-40°C to +100°C
-65°C to +150°C
260°C for 5 Sec.
Recommended Operating Conditions
Parameter
Typ
Units
Parameter
Typ
Units
Collector Voltage (+Vcc)
Reference Voltage (Vref)
(Fixed and regulated)
3.2 to 4.1
+2.95 (±1.2%)
Volts
Volts
Operating Temperature (PC Board)
-20 to +70
°C
Application Information
The CHP0230-PM is a two-stage amplifier that requires a
single regulated positive supply along with the unregulated bat-
tery voltage for proper operation. Vref is a regulated 2.95 refer-
ence voltage for the bias control circuitry. It can also be used as
a power down mode select. Vcc is an unregulated supply volt-
age directly from the battery. Vcc should be applied prior to
Vref and before RF input power. The CHP0230-PM can be
operated over a range of supply voltages and bias points by
adjustment of Vref. It is important that the maximum power
dissipation of the package be observed at all times and that the
maximum voltage across the device is not exceeded.
3236 Scott Boulevard
Santa Clara, California 95054
Circuit Design Considerations
Biasing
The positive Vcc supply voltages are applied to pins
1 and 6. Most bypass decoupling is provided on-board. Vref is
applied to pin 3.
The recommended DC bypass capacitance is shown in the
schematic diagram on Page 4.
Inadequate bypass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), reduce power gain and/or create oscillations.
– Continued on Page 2 –
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Electrical Characteristics
Product Specifications - July 2002
(2 of 4)
TM
Unless otherwise specified, the following specifications are guaranteed at room temperature with collector voltage (+Vcc) = 3.6 V.
Parameter
Condition
Min
Typ
Max
Units
Frequency Range
Gain
Gain Ripple*
Gain Variation
Power Output
Harmonics
Noise Power in Receive Band
Linearity (ACPR)
@ Digital power output
824-849 MHz
Over supply voltage
Over temperature
CDMA mode
Analog
2nd @ Po = +31.5 dBm
3rd @ Po = +31.5 dBm
30 kHz bandwidth
CDMA mode @ +28.5 dBm Pout, 885 kHz offset
CDMA mode @ +28.5 dBm Pout, 1.9 MHz offset
CDMA2K 1X mode** @ +27.8 dBm Pout, 885 kHz offset
CDMA2K 1X mode** @ +27.8 dBm Pout, 1.9 MHz offset
824
29
30
2
0.03
+28.5
+31.0
-30
-30
-90
-52
-59
-49
-58
4.0
-10
105
515
750
60
2.0
2.95
849
33
1.5
Noise Figure
Input Return Loss
Icc (Vcc = 3.6 V)
-47
-56
-47
-56
5.0
112
560
815
5.0
10
Quiescent Current (Iq)
Vref Supply Current (Iref)
Vref Supply Voltage (Vref)
Leakage Current
Pout = +12.0 dBm - CDMA mode
Pout = +28.5 dBm - CDMA mode
Pout = +31.5 dBm - Analog mode
No RF
Fixed and regulated (1.2% tolerance)
Vref = 0 V, Vcc = 3.6 V
MHz
dB
dB
dB/V
dB/°C
dBm
dBm
dBc
dBc
dBm
dBc/30KHz
dBc/30KHz
dBc/30KHz
dBc/30KHz
dB
dB
mA
mA
mA
mA
mA
V
µA
* Specifications guaranteed over the temperature range of -20°C to +70°C. ** Modulation HPSK in 1.2288 MHz, RC3 PAR = 4.7 @ 1% CCDF.
– Continued from Page 1 –
Modulation
When biased as specified, the CHP0230-PM will
achieve the required adjacent channel response for the digital
system specified. Celeritek tests 100% of each product under
digital modulation to ensure correlation to customer applica-
tions.
Thermal
1. The ground pad on the backside of the CHP0230-PM must
be soldered to the ground plane.
2. All leads of the package must be soldered to the appropriate
electrical connection.
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Product Specifications - July 2002
(3 of 4)
TM
Product Consistency Distribution
Note: Unless otherwise specified, the following data was taken at 836 MHz.
Current
(Analog)
@ 3.6 V, Pout = 31.5 dBm
10000 –
MEAN
USL
-3sp
6000 –
+3sp
5000 –
4000 –
3000 –
2000 –
2000 –
1000 –
0–
0.68
0–
0.7
0.72
0.74 0.76 0.78
Amps
0.8 0.82
0.48
7000 –
6000 –
8000 –
Current
(CDMA)
@ 3.6 V, Pout = 28.5 dBm
MEAN
USL
-3sp
+3sp
4000 –
0.5
0.52
Amps
0.54
0.56
0.58
Gain
(Analog)
@ 3.6 V, Pout = 31.5 dBm
7000 –
6000 –
5000 –
4000 –
3000 –
2000 –
1000 –
0–
26
27
28
29
dB
30
31
32
33
LSL
-3sp
+3sp
MEAN
3000 –
USL
2500 –
2000 –
1500 –
1000 –
500 –
Gain
(CDMA)
@ 3.6 V, Pout = 28.5 dBm
MEAN
USL
+3sp
LSL
-3sp
0–
28.5 29
29.5 30 30.5
dB
31 31.5
32
32.5
Linearity
(ACPR)
@ 3.6 V, Pout = 28.5 dBm
(±885 MHz)
8000 –
MEAN
USL
6000 –
-3sp
+3sp
Linearity
(ACPR)
@ 3.6 V, Pout = 28.5 dBm
(±1.98 MHz)
6000 –
5000 –
-3sp
4000 –
+3sp
MEAN
4000 –
3000 –
2000 –
2000 –
1000 –
0–
-56
-52
-52
dBc
-50
-48
-46
0–
-64
-63
-62
-61
-60
dBc
-59
-58
-57
-56
3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Recommended Application Circuit
Note: This schematic represents the topology of the application cir-
cuit recommended by Celeritek.
Product Specifications - July 2002
(4 of 4)
TM
PCB Footprint
(Minimum Pad Dimensions)
0.295 (7.50)
0.100 (2.55)
Vcc
10 µF
1
2
50Ω
Vref
3.3 µF
3
T1
6
CHP0230-PM
5
220 pF
4
N/C
50Ω
RF OUT
0.032 (0.80)
MIN. X6
RF IN
0.240
(6.10)
0.015 (0.38) DIA.
VIA HOLE X21
0.015 (0.40)
RADIUS
X12
T1 line is important to ensure best bypassing. Optimum performance
is achieved through an electrical length of 20°min. at 835 MHz.
Evaluation Board Schematic
Board substrate:
ER = 4.60
Thickness = 0.031 in.
0.054 (1.36) X4
0.060 (1.50) MIN.
DIMENSIONS IN INCHES (mm)
DRAWING NOT TO SCALE
Physical Dimensions
Ordering Information
The CHP0230-PM is available in a surface mount 50 ohm matched module and devices are available in tube or tape and reel.
Package
Part Number for Ordering
CHP0230-PM-0000
PM6 surface mount power package in tube
CHP0230-PM-000T
PM6 surface mount power package in tape and reel
PB-CHP0230-PM
Evaluation Board with SMA connectors for CHP0230-PM
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Celeritek does not convey any license under its patent
rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent
regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
3236 Scott Boulevard, Santa Clara, California 95054
