CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
June 1999
N
CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
General Description
The CLC440 is a wideband, low-power, voltage feedback op amp
that offers 750MHz unity-gain bandwidth, 1500V/µs slew rate, and
90mA output current. For video applications, the CLC440 sets new
standards for voltage feedback monolithics by offering the impres-
sive combination of 0.015% differential gain and 0.025° differen-
tial phase errors while dissipating a mere 70mW.
The CLC440 incorporates the proven properties of Comlinear’s
current feedback amplifiers (high bandwidth, fast slewing, etc.) into a
“classical” voltage feedback architecture. This amplifier possesses
truly differential and fully symmetrical inputs both having a high
900kΩ impedance with matched low input bias currents.
Furthermore, since the CLC440 incorporates voltage feedback, a
specific R
f
is not required for stability. This flexibility in choosing R
f
allows for numerous applications in wideband filtering and integration.
Unlike several other high-speed voltage feedback op amps, the
CLC440 operates with a wide range of dual or single supplies
allowing for use in a multitude of applications with limited supply
availability. The CLC440’s low 3.5nV/√Hz(e
n
) and 2.5pA/√Hz(i
n
)
noise sets a very low noise floor.
Features
s
s
s
s
s
s
s
s
s
Unity-gain stable
High unity-gain bandwidth: 750MHz
Ultra-low differential gain: 0.015%
Very low differential phase: 0.025°
Low power: 70mW
Extremely fast slew rate: 1500V/µs
High output current: 90mA
Low noise: 3.5nV/√Hz
Dual ±2.5V to ±6V or single 5V to 12V supplies
Professional video
Graphics workstations
Test equipment
Video switching & routing
Communications
Medical imaging
A/D drivers
Photo diode transimpedance amplifiers
Improved replacement for CLC420 or OPA620
Frequency Response (A
V
= +2V/V)
Applications
s
s
s
s
s
s
s
s
s
Typical Application
10MHz to 40MHz Square and Triangular Wave Generator
Generator Waveforms
Pinout
DIP & SOIC
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
CLC440 Electrical Characteristics
(A
V
= +2, R
f
= R
g
= 250Ω: V
cc
= + 5V, R
L
= 100Ω unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC440
TYP
+25˚C
260
190
750
230
0.05
0.8
0.015
0.025
1.5
3.2
10
7
1500
-64
-52
-70
-51
3.5
2.5
1.0
5.0
10
30
0.5
3.0
65
80
7.0
MIN/MAX RATINGS
+25˚C
0 to 70˚C -40 to 85˚C
165
150
0.15
1.2
0.03
0.05
2.0
4.2
14
13
900
-59
-46
-65
-45
4.5
3.5
3.0
30
2.0
58
65
7.5
165
135
0.20
1.5
0.04
0.06
2.2
4.5
16
13
750
-59
-46
-64
-43
5.0
4.0
3.5
10
35
50
2.0
10
58
60
8.0
135
130
0.20
1.5
0.04
0.06
2.5
5.0
16
13
600
-59
-46
-64
-43
5.0
4.0
4.0
10
40
60
3.0
10
58
60
8.0
UNITS
NOTES
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth A
V
=+2
V
out
< 0.2V
pp
V
out
< 4.0V
pp
-3dB bandwidth A
V
=+1
V
out
< 0.2V
pp
gain bandwidth product
V
out
< 0.2V
pp
gain flatness
V
out
< 2.0V
pp
DC to 75MHz
linear phase deviation
V
out
< 2.0V
pp
DC to 75MHz
differential gain
4.43MHz, R
L
=150Ω
differential phase
4.43MHz, R
L
=150Ω
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
2V step
4V step
2V step
4V step
4V step, ±0.5V crossing
MHz
MHz
MHz
MHz
dB
deg
%
deg
ns
ns
ns
%
V/µs
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
A
A
A
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2V
pp
, 5MHz
2V
pp
, 20MHz
3rd harmonic distortion
2V
pp
, 5MHz
2V
pp
, 20MHz
equivalent input noise
voltage
>1MHz
current
>1MHz
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input offset current
average drift
power supply rejection ratio
common-mode rejection ratio
supply current
DC
DC
R
L
=
∞
A
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
input capacitance
common-mode
differential-mode
input voltage range
common-mode
output voltage range
R
L
= 100Ω
output voltage range
R
L
=
∞
output current
900
1.2
0.5
±3.0
±2.5
±3.0
±80
500
2.0
1.0
±2.8
±2.3
±2.8
±72
400
2.0
1.0
±2.7
±2.2
±2.7
±65
300
2.0
1.0
±2.7
±2.2
±2.7
±45
kΩ
pF
pF
V
V
V
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
voltage supply
I
out
is short circuit protected to ground
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human bodey model)
±6V
±Vcc
+150˚C
-65˚C to +150˚C
+300˚C
<1000V
Model
CLC440AJP
CLC440AJE
CLC440A8B
Ordering Information
Temperature Range
-40
˚
C to +85
˚
C
-40
˚
C to +85
˚
C
-55
˚
C to +125
˚
C
Description
8-pin PDIP
8-pin SOIC
8-pin hermetic CerDIP,
MIL-STD-883
Contact factory for SMD number.
Package Thermal Resistance
Package
Plastic (AJP)
Surface Mount (AJE)
CerDip
θ
jc
70
˚
/W
60
˚
/W
40
˚
/W
θ
ja
125
˚
/W
140
˚
/W
130
˚
/W
Transitor Count
Notes
A) J-level: spec is 100% tested at +25˚C.
46
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2
CLC440 Typical Performance Characteristics
(A
V
= +2, R
f
= 250Ω:V
cc
= + 5V, R
L
= 100Ω unless specified)
Non-Inverting Frequency Response
A
V
= 1(R
f
= 0)
Gain
Gain
Inverting Frequency Response
A
V
= -1
Frequency Response vs. Load
R
L
=1K
Gain
Magnitude (1dB/div)
Magnitude (1dB/div)
A
V
= 5
A
V
= 10
Phase
A
V
= 2
A
V
= 2
A
V
= -10
(Rf = 500Ω)
A
V
= -5
Phase
A
V
-1
A
V
= -2
Magnitude (1dB/div)
R
L
=100
Phase (deg)
Phase (deg)
Phase (deg)
R
L
=50
Phase
R
L
=1K
R
L
=50
A
V
= 1
A
V
= 10
A
V
= 5
0
-45
-90
-135
-180
-180
-225
-270
-315
-360
0
-45
-90
-135
-180
A
V
-10
A
V
-5
A
V
-2
R
L
=100
1
10
100
1000
1
10
100
1000
1
10
100
1000
Frequency (MHz)
Frequency Response vs. V
out
V
out
= 200mV
pp
Gain
Gain
Frequency (MHz)
Frequency Response vs. Capacitive Load
C
L
= 10pF
R
s
= 50
Frequency (MHz)
Gain Flatness and Linear Phase
Magnitude (0.05dB/div)
Gain
Magnitude (1dB/div)
Magnitude (1dB/div)
Phase (1.0deg/div)
V
out
= 2V
pp
V
out
= 5V
pp
Phase
V
out
= 2V
pp
C
L
= 1000pF
R
s
= 5
Phase
C
L
= 100pF
C
L
= 100pF
R
s
= 30
C
L
= 10pF
Phase (deg)
Phase (deg)
0
-45
-90
-135
-180
1000
0
-45
-90
C
L
= 1000pF
+
-
Phase
V
out
= 5V
pp
R
s
C
L
1k
V
out
= 200mV
pp
-135
-180
1
10
100
1
10
100
1000
0
75
Frequency (MHz)
Open Loop Gain and Phase
80
Gain
Frequency (MHz)
BW vs. Gain for Transimpedance Configuration
0
Cd = 1pF
C
f
Frequency (7.5MHz/div)
Equivalent Input Noise
400
320
10
10
Noise Voltage (nV/
√
Hz)
Noise Current (pA/
√
Hz)
Open Loop Gain (dB)
60
4
Example
Bandwidth (MHz)
Phase (deg)
C
f
(pF)
40
Phase
0
-90
8
R
f
C
f
1.6
BW
123
Cd = 5pF
1000
240
160
80
Voltage = 3.5nV/√Hz
See dashed lines
20
0
-20
1k
10k
100k
1M
10M
12
Current = 2.5pA/√Hz
-180
-270
100M
16
Cd = 20pF
BW
20
100
1000
0
10000
1
100
1k
10k
100k
1M
10M
1
100M
Frequency (Hz)
Harmonic Distortion vs. Frequency
-45
-55
V
o
= 2V
pp
R
f
1dB Compression
45
5MHz
CMRR
Frequency (Hz)
PSRR, CMRR, and Closed Loop R
out
100
80
PSRR
20MHz
PSRR/CMRR (dB)
35
25
15
5
Distortion (dBc)
Gain (1dB/div)
R
out
(Ω)
-65
-75
-85
-95
0.1
1
10
50
60
40
20
50MHz
P
out
50Ω
2nd R
L
= 100
3rd R
L
= 100
2nd R
L
= 1k
3rd R
L
= 1k
+
-
50Ω
250Ω
100MHz
250Ω
R
out
0
-4
0
4
8
12
16
10k
100k
1M
10M
100M
Frequency (MHz)
Input and Output VSWR
Input
Output Power (P
out
)
2-Tone, 3rd Order Intermodulation Intercept
50
Frequency (Hz)
Differential Gain and Phase
Differential Gain (%), Phase (deg)
0.12
2.2
50Ω
+
-
Intercept Point (+dBm)
50Ω
250Ω
Output
40
30
Phase
Positive Sync
1.8
50Ω
VSWR
1.4
1.0
Output
Input
Gain
Negative Sync
0.08
20
+
-
50Ω
250Ω
50Ω
P
out
10
0
Phase
Negative Sync
Gain
Positive Sync
0.04
250Ω
0
2
3
4
0
40
80
120
160
200
1
10
100
1
Frequency (20MHz/div)
Frequency (MHz)
Number of 150Ω Loads
3
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CLC440 Typical Performance Characteristics
(A
V
= +2, R
f
= 250Ω:V
cc
= + 5V, R
L
= 100Ω unless specified)
Pulse Response
2.0
0.4
Typical DC Errors vs. Temperature
6
2
l
os
0.05% Settling Time vs. Capacitive Load
80
55
R
s
Input Bias, Offset Current, l
b
l
os
(µA)
A
V
= +2
Settling Time, T
s
(ns) to 0.05%
Input Offset Voltage, V
io
(mV)
Output Voltage (0.5V/div)
Recommended R
s
(Ω)
1.0
0
-0.4
-0.8
-1.2
-1.6
l
b
V
io
60
45
-2
-6
-10
+
0
40
R
s
C
L
1k
-
35
-1.0
A
V
= -2
20
T
s
25
-2.0
-14
-60
-20
20
60
100
140
0
10
100
Time (5ns/div)
15
1000
Temperature (C°)
Short Term Settling Time
Settling Error % of Output Step
Settling Error % of Output Step
0.2
0.2
Load Capacitance C
L
(pF)
I
b
and I
os
vs. Common-Mode Voltage
Offset Current, I
os
(5nA/div)
20
10
0
-10
-20
-4.0
-2.4
-0.8
0.8
2.4
4.0
2.0
1.0
0
Long Term Settling Time
Bias Current, I
b
(0.5µA/div)
0.1
0.1
I
b
0
0
l
os
-0.1
-0.1
-1.0
-2.0
-0.2
0
20
40
60
80
100
-0.2
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Time (ns)
Time (s)
Common-Mode Input Voltage (V)
APPLICATION INFORMATION
General Design Equations
The CLC440 is a unity gain stable voltage feedback
amplifier. The matched input bias currents track well over
temperature. This allows the DC offset to be minimized
by matching the impedance seen by both inputs.
Gain
The non-inverting and inverting gain equations for the
CLC440 are as follows:
Non-inverting Gain: 1
+
Inverting Gain:
−
R
f
R
g
R
f
R
g
Output Drive and Settling Time Performance
The CLC440 has large output current capability. The
90mA of output current makes the CLC440 an excellent
choice for applications such as:
•
Video Line Drivers
•
Distribution Amplifiers
When driving a capacitive load or coaxial cable, include a
series resistance Rs to back match or improve settling
time. Refer to the “Settling Time vs. Capacitive Load” plot
in the typical performance section to determine the
recommended resistance for various capacitive loads.
When driving resistive loads of under 500Ω, settling time
performance diminishes. This degradation occurs
because a small change in voltage on the output causes
a large change of current in the power supplies. This
current creates ringing on the power supplies. A small
resistor will dampen this effect if placed in series with the
6.8µF bypass capacitor.
Noise Figure
Noise Figure (NF) is a measure of noise degradation
caused by an amplifier.
e
ni2
S
i
/N
i
NF
=
10LOG
=
10LOG
2
S
o
/N
o
e
t
where,
e
ni
= Total Equivalent Input Noise Density
Due to the Amplifier
e
t
= Thermal Voltage Noise ( 4kTR
seq
)
4
Gain Bandwidth Product
The CLC440 is a voltage feedback amplifier, whose
closed-loop bandwidth is approximately equal to the
gain-bandwidth product (GBP) divided by the gain (Av).
For gains greater than 5, Av sets the closed-loop band-
width of the CLC440.
Closed Loop Bandwidth =
A
v
GBP
A
v
(
R
f
+
R
g
)
=
R
g
GBP = 230MHz
For gains less than 5, refer to the frequency response
plots to determine maximum bandwidth.
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Figure 1 shows the noise model for the non-inverting
amplifier configuration. The model includes all of the
following noise sources:
Noise Figure vs. Source Resistance
25
R
s
(Ω) NF Unterminated NF Terminated
50
12.03dB
3.13dB
17.90dB
6.15dB
•
•
•
Input voltage noise (e
n
)
Input current noise (i
n
= i
n+
= i
n-
)
Thermal Voltage Noise (e
t
) associated with each
external resistor
e
n
R
seq
4kTRseq
Noise Figure (dB)
20
15
10
Unterminated
R
OPT
Terminated
R
opt
= 2800Ω
*
*
*
i
n+
*
+
CLC440
5
0
R
opt
= 1400Ω
-
R
f
i
n-
R
g
4kTRf
10
100
1k
10k
100k
*
Source Resistance (Ω)
Figure 2: Noise Figure vs. Source Resistance
These boards were laid out for optimum, high-speed
performance. The ground plane was removed near the
input and output pins to reduce parasitic capacitance.
And all trace lengths were minimized to reduce series
inductances.
Supply bypassing is required for the amplifiers
performance. The bypass capacitors provide a low
impedance return current path at the supply pins. They
also provide high frequency filtering on the power supply
traces. 6.8µF tantalum, 0.01µF ceramic, and 500pF
ceramic capacitors are recommended on both supplies.
Place the 6.8µF capacitors within 0.75 inches of the
power pins, and the 0.01µF and 500pF capacitors less
than 0.1 inches from the power pins.
Dip sockets add parasitic capacitance and inductance
which can cause peaking in the frequency response and
overshoot in the time domain response. If sockets are
necessary, flush-mount socket pins are recommended.
The device holes in the 730055 evaluation board are
sized for Cambion P/N 450-2598 socket pins, or their
functional equivalent.
*
4kTRg
R
seq
= R
s
for Unterminated Systems
R
seq
= R
s
II R
T
for Terminated Systems
Figure 1: Non-inverting Amplifier Noise Model
The total equivalent input noise density is calculated
by using the noise model shown. Equations 1 and 2
represent the noise equation and the resulting equation
for noise figure.
2
e
ni
=
e
n2
+
i
n2
R
seq2
+
R
f
IIR
g
+
4kTR
seq
+
4kT R
f
IIR
g
(
)
(
)
Equation 1: Noise Equation
2
2
e
n
+
i
n2
R
seq2
+
R
f
IIR
g
+
4kTR
seq
+
4kT R
f
IIR
g
NF
=
10LOG
4kTR
seq
(
)
(
)
Equation 2: Noise Figure Equation
The noise figure is related to the equivalent source
resistance (R
seq
) and the parallel combination of R
f
and
R
g.
To minimize noise figure, the following steps are
recommended:
Applications Circuits
Transimpedance Amplifier
The low 2.5pA/√Hz input current noise and unity gain
stability make the CLC440 an excellent choice for
transimpedance applications. Figure 3 illustrates a
low noise transimpedance amplifier that is commonly
implemented with photo diodes. R
f
sets the transimped-
ance gain. The photo diode current multiplied by R
f
determines the output voltage.
C
f
R
f
Photo Diode
Representation
•
Minimize R
f
IIR
g
•
Choose the optimum R
s
(R
OPT
)
R
OPT
is the point at which the NF curve reaches a
minimum and is approximated by:
e
R
OPT
≅
n
i
n
Figure 2 is a plot of NF vs R
s
with R
f
= 0, R
g
=
∞
(A
v
= +1).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes R
s
= R
T
. The table indicates the NF for various source resis-
tances including R
s
= R
OPT
.
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC440 (CLC730055-DIP,
CLC730060-SOIC) and suggests their use as a guide for
high frequency layout and as an aid in device testing and
characterization.
5
-
CLC440
V
out
I
in
C
d
+
V
out
= -I
in
*R
f
Figure 3: Transimpedance Amplifier Configuration
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