MATRA MHS
M 67025
8 K
×
16 CMOS Dual Port RAM
Introduction
The M 67025 is a very low power CMOS dual port static
RAM organised as 8192
×
16. The M 67025 is designed
to be used as a stand-alone 16 bit dual port RAM or as a
combination MASTER/SLAVE dual port for 32 bit or
more
width
systems.
The
MATRA-MHS
MASTER/SLAVE dual port approach in memory system
applications results in full speed, error free operation
without the need of an additional discrete logic.
Master and slave devices provide two independant ports
with separate control, address and I/O pins that permit
independant, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the on-chip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eigh transistors (8T) memory cell and
fabricated with the state of the art 0.65
µ
lithography
named SCMOS, the M 67025 combines an extremely low
standby supply current (typ = 1.0
µA)
with a fast access
time at 20 ns over the full temperature range. All versions
offer battery backup data retention capability with a
typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the M 67025 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D
Fast access time : 20/25/30/35/45/55 ns
D
Wide temperature range :
–55
°C
to +125
°C
D
67025 L low power
67025 V very low power
D
Separate upper byte and lower byte control for multiplexed
bus compatibility
D
Expandable data bus to 32 bits or more using master/slave
chip select when using more than one device
D
On chip arbitration logic
D
Versatile pin select for master or slave :
– M/S = H for busy output flag on master
– M/S = L for busy input flag on slave
D
INT flag for port to port communication
D
Full hardware support of semaphore signaling between ports
D
Fully asynchronous operation from either port
D
Battery back-up operation : 2 V data retention
D
TTL compatible
D
Single 5 V
±
10 % power supply
D
For 3.3 V version, please consult sales
Rev. D (29/09/95)
1
M 67025
Interface
Block Diagram
MATRA MHS
Note :
1. (MASTER) : BUSY is output. (SLAVE) : BUSY is input.
2. LB = Lower Byte
UB = Upper Byte
Pin Names
LEFT PORT
CS
L
R/W
L
OE
L
A
0L – 12L
I/O
0L – 15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
Vcc
GND
RIGHT PORT
CS
R
R/W
R
OE
R
A
0R – 12R
I/O
0R – 15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
NAMES
Chip select
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2
Rev. D (29/09/95)
MATRA MHS
M 67025
Functional Description
Pin Configuration
Top View
Rev. D (29/09/95)
3
M 67025
Pin Configuration
SEM
L
I/O
2L
R/W
L
I/O
7L
I/O
4L
I/O
3L
I/O
0L
OE
L
I/O
6L
I/O
5L
GND
I/O
1L
A
9L
A
8L
Vcc
INDEX
A
10L
CE
L
LB
L
N/C
A
11L
UB
L
MATRA MHS
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
Vcc
GND
I/O
0R
I/O
1R
I/O
2R
Vcc
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1
63
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
67025
F-84-2
84-PIN MQFPF
FLATPACK
TOP VIEW
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
21
43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
I/O
9R
I/O
10R
UB
R
LB
R
N/C
A
11R
CE
R
I/O
12R
I/O
13R
SEM
R
A
10R
A
11L
GND
I/O
11R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
A
8R
A
7R
A
8L
A
9R
A
10L
OE
L
Vcc
R/W
L
SEM
L
CE
L
I/O
2L
I/O
9L
I/O
7L
I/O
4L
I/O
3L
I/O
0L
I/O
8L
I/O
6L
I/O
5L
GND
I/O
1L
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
Vcc
GND
I/O
0R
I/O
1R
I/O
2R
Vcc
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O
10R
I/O
11R
GND
SEM
R
I/O
12R
LB
R
A
12R
CE
R
UB
R
GND
I/O
15R
A
10R
OE
R
A
11R
I/O
8R
I/O
13R
I/O
14R
I/O
9R
R/W
R
A
8R
A
7R
A
6R
A
5R
A
9R
67025
100-PIN TQFP
TOP VIEW
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
6L
A
9L
A
7L
INDEX
UB
L
LB
L
A
12L
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
4
I/O
7R
Rev. D (29/09/95)
MATRA MHS
M 67025
if the CSs are low before an address match, on-chip
control logic arbitrates between the left and right
addresses for access (refer to table 4). The inhibited port’s
BUSY flag is set and will reset when the port granted
access completes its operation in both arbitration modes.
Functional Description
The M 67025 has two ports with separate control, address
and I/0 pins that permit independent read/write access to
any memory location. These devices have an automatic
power-down feature controlled by CS.CS controls
on-chip power-down circuitry which causes the port
concerned to go into stand-by mode when not selected
(CS high). When a port is selected access to the full
memory array is permitted. Each port has its own Output
Enable control (OE). In read mode, the port’s OE turns the
Output drivers on when set LOW. Non-conflicting
READ/WRITE conditions are illustrated in table 1.
The interrupt flag (INT) allows communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INT
L
)
is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading
address location 1FFE. Similarly, the right port interrupt
flag (INT
R
) is set when the left port writes to memory
location 1FFF (HEX), and the right port must read
memory location 1FFF in order to clear the interrupt flag
(INT
R
). The 16 bit message at 1FFE or 1FFF is
user-defined. If the interrupt function is not used, address
locations 1FFE and 1FFF are not reserved for mail boxes
but become part of the RAM. See table 3 for the interrupt
function.
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 32 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chips has a hardware
arbitrator, and the addresses for each arrive at the same
time one chip may activate in L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developped a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to the
MASTER with no external components, giving a speed
advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until after
the BUSY input has settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation.
Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the
conflict is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is
active at the same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Arbitration Logic
Functional Description
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns determine
which port has access. In all cases, an active BUSY flag
will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously. Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
logic arbitrates between CS
L
and CS
R
for access ; or (2)
Semaphore Logic
Functional Description
The M 67025 is an extremely fast dual-port 4k
×
16
CMOS static RAM with an additional locations dedicated
to binary semaphore flags. These flags allow either of the
processors on the left or right side of the dual-port RAM
to claim priority over the other for functions defined by
the system software. For example, the semaphore flag can
be used by oner processor to inhibit the other from
accessing a portion of the dual-port RAM or any other
shared resource.
Rev. D (29/09/95)
5
