Cal-Chip
C
ONSTRUCTION
F
EATURES
Electronics, Incorpor
at
ed
CN S
ERIES
Thick Film Chip Resistor Arrays
• High Density
• Automatic Placement
D
IMENSIONS
Unit: mm
TYPE
CN34
CN35
CN64
CN65
L
3.2±0.1
5.2±0.2
6.4±0.2
W
1.6±0.1
3.1±0.2
t
0.55±0.1
0.55±0.1
P
0.8±0.1
0.64±0.05
1.27±0.05
a
0.45±0.05
0.35±0.1
0.8±0.2
b
0.3±0.2
0.5±0.2
c
0.3±0.2
0.5±0.2
R
ATING
TYPE
CN34
CN35
CN64
CN65
Power
Rating
at 70°C
1/16W
1/16W
1/8W
1/8W
Max
Working
Voltage
25V
50V
Max.
Overload
Voltage
50V
-55~+125°C
100V
Operating
Temp. (°C)
Resistance
Tolerance
F±1%
J±5%
Resistance
Range (Ω)
Temp
Coefficient
ppm/°C
10Ω~1MΩ
±200ppm/°C
O
RDERING
I
NFORMATION
CN
Chip Resistor
Networks/Arrays
Series
34-0603x4
35-0603x5
64-1206x4
65-1206x5
34
J
103
CT
Packaging
Nominal Resistance
8P4R
10P8R
8P4R
10P8R
Resistance Tolerance
J = ±5%
F = ±1%
65
Cal-Chip
Electronics,
In
c
or
porated
CN S
ERIES
Thick Film Chip Resistor Arrays
1.0 Number of Element
Depend on its element’s number. (2-2 element. 4-4 element)
2.0 Resistance Tolerance
F: ±1%
J: ±5%
3.0 Nominal Resistance
Example: 103, 10 is effective digit, 3 is a multiple which represents the cube of 10, zero number is three.
4.0 Schematics
R
1
= R
2
= R
3
= R
4
5.0 Power Derating Curve
The resistors operated in ambient temperatures above 70°C, power rating must be derated in accordance
with the curve in Figure 1.
5.1 Rated Voltage
The value of rated voltage shall be determined from formula (1).
E =
√P
x R........(1)
E =Rated Voltage (V)
P = Power Rating (W)
R = Nominal Resistance (Ω)
6.0 Electrical / Machine Characteristics and Test Methods
Item
Specifications
Temperature Coefficient
Short Time Overload
TCR: ±200 ppm
±(2%+0.05Ω)
Inspection Temp.
Test Methods
Cold: +25°C~55°C
Hot: +25°C~+125°C
1. Apply 2.5 x rated voltage for 5 sec.
2. Wait 30 minutes
3. Measure resistance value
1. Dwell in chamber at 70±2°C for ON: 90 min. at
rated voltage; then OFF: 30 min.
2. Perform 1,000 hours cyclically
1. Dwell in humidity chamber at 40 ±2°C and 95% RH for
ON: 90 min. at rated voltage; then OFF: 30 min.
2. Perform 1,000 hours cyclically
1. -55±3°C~125±3°C, make 5 cycles.
2. Released 1 hour in room temp., then measure value.
1. Immersed in molten solder at 270±5°C for 10±.01 sec.
2.Released 1 hour in room temp., then measure value.
1. Immersed in rosin solution for 5-10 seconds.
2. Re-immersed in solder pot at 230±5°C for 3±0.5 sec
1. Perform 10,000 voltage cycles as follows: ON (2.5 x rated
voltage or current) 1 sec. and OFF 25 sec.
2. Released 30 min. without loading.
3. Measure resistance.
Apply 300VAC for 1 second
Apply 100VDC.
Load Life
±(3%+0.05Ω)
Load Life in Humidity
Temperature Cycling
Effect of Soldering
Solderability
Intermittent Overload
±(3%+0.05Ω)
±(1 %+0.05Ω)
±(2.5%+0.05Ω)
Non-damage by machinery
95% coverage min.
±(5%+0.1Ω)
Dielectric Withstanding Voltage
Insulation Resistance
No evidence of mechanical damage
10
8
Ω
min
66
Cal-Chip
Electronics, Incorpor
at
ed
CN S
ERIES
Thick Film Chip Resistor Arrays
T
APING
S
PECIFICATION
Carrier Tape
Unit in mm
PaperTape
Type
CN34
CN35
5,000
A
2.0±0.2
B
3.6±0.2
C
D
E
F
G
H
J
1.5±0.1
t
1.0
8.0±0.1 3.5±0.05
1.75±0.1 4.0±0.1 2.0±0.05 4.0±0.1
Plastic Concave-Tape
CN64
CN65
4,000
3.5±0.1
3.5±0.1
5.5±0.1
6.75±0.1
12.0±0.1 5.5±0.05
1.75±0.1 4.0±0.1 2.0±0.05 4.0±0.1
1.5±0.1
1.0
67
Cal-Chip
Electronics,
In
c
or
porated
CN S
ERIES
Thick Film Chip Resistor Arrays
The top fixed tape for each carrier shall have an adhesion peel strength of 10 to 50g, measure methods is
shown below to peel away.
CARRIER TAPE
TOP COVER TAPE
TO PEEL AWAY
(ABOUT 200 mm/min)
10°
TO PEEL AWAY
TAPE REEL
Type
CN34
CN35
CN64
CN65
A
φ178±2.0
φ178±2.
0
B
φ80±2.0
φ80±2.0
C
φ13±0.5
φ13±0.2
D
φ21.0
φ21.0
E
2.0±0.5
2.0±0.5
W1
10.0±1.0
13.5±1.0
W2
12.5±1.0
15.5±1.0
68
