COP8CBE9/CCE9/CDE9 8-Bit CMOS Flash Based Microcontroller with 8k Memory, Virtual
EEPROM, 10-Bit A/D and Brownout Reset
PRELIMINARY
April 2002
COP8CBE9/CCE9/CDE9
8-Bit CMOS Flash Microcontroller with 8k Memory,
Virtual EEPROM, 10-Bit A/D and Brownout Reset
General Description
The COP8CBE9/CCE9/CDE9 Flash microcontrollers are
highly integrated COP8
™
Feature core devices, with 8k
Flash memory and advanced features including Virtual EE-
PROM, A/D, High Speed Timers, USART, and Brownout
Reset. This single-chip CMOS device is suited for applica-
Devices included in this datasheet:
Device
COP8CBE9
COP8CCE9
Flash Program
Memory (bytes)
8k
8k
RAM
(bytes)
256
256
Brownout
Voltage
2.7V to 2.9V
4.17V to 4.5V
I/O
Pins
37,39
37,39
Packages
44 LLP, 44PLCC,
48 TSSOP
44 LLP, 44PLCC,
48 TSSOP
44 LLP,
44 PLCC,
48 TSSOP
Temperature
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +125˚C
0˚C to +70˚C
−40˚C to +125˚C
tions requiring a full featured, in-system reprogrammable
controller with large memory and low EMI. The same device
is used for development, pre-production and volume produc-
tion with a range of COP8 software and hardware develop-
ment tools.
COP8CDE9
8k
256
No Brownout
37,39
Features
KEY FEATURES
n
8k bytes Flash Program Memory with Security Feature
n
Virtual EEPROM using Flash Program Memory
n
256byte volatile RAM
n
10-bit Successive Approximation Analog to Digital
Converter (up to 16 channels)
n
100% Precise Analog Emulation
n
USART with onchip baud generator
n
2.7V – 5.5V In-System Programmability of Flash
n
High endurance -100k Read/Write Cycles
n
Superior Data Retention - 100 years
n
Dual Clock Operation with HALT/IDLE Power Save
Modes
n
Two 16-bit timers:
— Timer T2 can operate at high speed (50 ns
resolution)
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n
Brown-out Reset (COP8CBE9/CCE9)
n
High Current I/Os
— B0– B3: 10 mA
@
0.3V
— All others: 10 mA
@
1.0V
OTHER FEATURES
n
Single supply operation:
— 2.7V–5.5V (0˚C to +70˚C)
— 4.5V–5.5V (−40˚C to +125˚C)
n
Quiet Design (low radiated emissions)
n
Multi-Input Wake-up with optional interrupts
n
MICROWIRE/PLUS (Serial Peripheral Interface
Compatible)
n
Clock Doubler for 20 MHz operation from 10 MHz
Oscillator, with 0.5 µs Instruction Cycle
n
Eleven multi-source vectored interrupts servicing:
— External Interrupt
— USART (2)
— Idle Timer T0
— Two Timers (each with 2 interrupts)
— MICROWIRE/PLUS Serial peripheral interface
— Multi-Input Wake-up
— Software Trap
n
Idle Timer with programmable interrupt interval
n
8-bit Stack Pointer SP (stack in RAM)
n
Two 8-bit Register Indirect Data Memory Pointers
n
True bit manipulation
n
WATCHDOG and Clock Monitor logic
n
Software selectable I/O options
— TRI-STATE Output/High Impedance Input
— Push-Pull Output
— Weak Pull Up Input
n
Schmitt trigger inputs on I/O ports
n
Temperature range: 0˚C to +70˚C and –40˚C to +125˚C
(COP8CCE9/CDE9)
n
Packaging: 44 PLCC, 44 LLP and 48 TSSOP
COP8
™
is a trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS200225
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COP8CBE9/CCE9/CDE9
Block Diagram
20022563
Ordering Information
Part Numbering Scheme
COP8
CB
Family and Feature Set
Indicator
CB = Low Brownout Voltage
CC = High Brownout Voltage
CD = No Brownout
E
Program
Memory
Size
E = 8k
9
Program
Memory
Type
9 = Flash
H
No. Of Pins
H = 44 Pin
I = 48 Pin
VA
Package
Type
LQ = LLP
MT = TSSOP
VA = PLCC
8
Temperature
7 = -40 to +125˚C
9 = 0 to +70˚C
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2
COP8CBE9/CCE9/CDE9
Connection Diagrams
20022564
Top View
Plastic Chip Package
See NS Package Number V44A
20022559
Top View
TSSOP Package
See NS Package Number MTD48
20022555
Top View
LLP Package
See NS Package Number LQA44A
3
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COP8CBE9/CCE9/CDE9
Pinouts for 44- and 48-Pin Packages
Port
L0
L1
L2
L3
L4
L5
L6
L7
G0
G1
G2
G3
G4
G5
G6
G7
H0
H1
H2
H3
H4
H5
H6
H7
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
DV
CC
DGND
AV
CC
AGND
CKI
RESET
I
I
RESET
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ADCH0
ADCH1
ADCH2
ADCH3
ADCH4
ADCH5
ADCH6
ADCH7
ADCH8
ADCH9
ADCH10
ADCH11
ADCH12
ADCH13 or A/D MUX OUT
ADCH14 or A/D MUX OUT
ADCH15 or A/DIN
V
CC
GND
36
37
38
39
40
41
24
25
26
27
28
29
30
31
35
32
34
33
15
6
31
32
33
34
35
36
19
20
21
22
23
24
25
26
30
27
29
28
10
1
Alt. Function
MIWU or Low Speed OSC In
MIWU or CKX or Low Speed OSC Out
MIWU or TDX
MIWU or RDX
MIWU or T2A
MIWU or T2B
MIWU
MIWU
INT
WDOUT
T1B
T1A
SO
SK
SI
CKO
a
In System
Emulation
Mode
44-Pin LLP
16
17
18
19
20
21
22
23
44-Pin PLCC
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
37
38
39
40
41
42
43
44
48-Pin
TSSOP
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
41
42
43
44
45
46
47
48
33
34
35
36
37
38
39
40
19
20
21
22
23
24
25
26
32
27
31
28
10
1
Input
POUT
Output
Clock
7
8
9
10
11
12
13
14
42
43
44
1
2
3
4
5
a. G1 operation as WDOUT is controlled by Option Register bit 2.
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COP8CBE9/CCE9/CDE9
1.0 General Description
1.1 EMI REDUCTION
The COP8CBE9/CCE9/CDE9 devices incorporate circuitry
that guards against electromagnetic interference - an in-
creasing problem in today’s microcontroller board designs.
National’s patented EMI reduction technology offers low EMI
clock circuitry, gradual turn-on output drivers (GTOs) and
internal Icc smoothing filters, to help circumvent many of the
EMI issues influencing embedded control designs. National
has achieved 15 dB–20 dB reduction in EMI transmissions
when designs have incorporated its patented EMI reducing
circuitry.
1.2 IN-SYSTEM PROGRAMMING AND VIRTUAL
EEPROM
The device includes a program in a boot ROM that provides
the capability, through the MICROWIRE/PLUS serial inter-
face, to erase, program and read the contents of the Flash
memory.
Additional routines are included in the boot ROM, which can
be called by the user program, to enable the user to custom-
ize in system software update capability if MICROWIRE/
PLUS is not desired.
Additional functions will copy blocks of data between the
RAM and the Flash Memory. These functions provide a
virtual EEPROM capability by allowing the user to emulate a
variable amount of EEPROM by initializing nonvolatile vari-
ables from the Flash Memory and occasionally restoring
these variables to the Flash Memory.
The contents of the boot ROM have been defined by Na-
tional. Execution of code from the boot ROM is dependent
on the state of the FLEX bit in the Option Register on exit
from RESET. If the FLEX bit is a zero, the Flash Memory is
assumed to be empty and execution from the boot ROM
begins. For further information on the FLEX bit, refer to
Section 4.5, Option Register.
1.3 DUAL CLOCK AND CLOCK DOUBLER
The device includes a versatile clocking system and two
oscillator circuits designed to drive a crystal or ceramic
resonator. The primary oscillator operates at high speed up
to 10 MHz. The secondary oscillator is optimized for opera-
tion at 32.768 kHz.
The user can, through specified transition sequences
(please refer to
7.0 Power Saving Features),
switch execu-
tion between the high speed and low speed oscillators. The
unused oscillator can then be turned off to minimize power
dissipation. If the low speed oscillator is not used, the pins
are available as general purpose bidirectional ports.
The operation of the CPU will use a clock at twice the
frequency of the selected oscillator (up to 20 MHz for high
speed operation and 65.536 kHz for low speed operation).
This doubled clock will be referred to in this document as
‘MCLK’. The frequency of the selected oscillator will be
referred to as CKI. Instruction execution occurs at one tenth
the selected MCLK rate.
1.4 TRUE IN-SYSTEM EMULATION
On-chip emulation capability has been added which allows
the user to perform true in-system emulation using final
production boards and devices. This simplifies testing and
evaluation of software in real environmental conditions. The
user, merely by providing for a standard connector which can
be bypassed by jumpers on the final application board, can
provide for software and hardware debugging using actual
production units.
1.5 ARCHITECTURE
The COP8 family is based on a modified Harvard architec-
ture, which allows data tables to be accessed directly from
program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently constant data tables need to be con-
tained in non-volatile memory, so they are not lost when the
microcontroller is powered down. In a modified Harvard ar-
chitecture, instruction fetch and memory data transfers can
be overlapped with a two stage pipeline, which allows the
next instruction to be fetched from program memory while
the current instruction is being executed using data memory.
This is not possible with a Von Neumann single-address bus
architecture.
The COP8 family supports a software stack scheme that
allows the user to incorporate many subroutine calls. This
capability is important when using High Level Languages.
With a hardware stack, the user is limited to a small fixed
number of stack levels.
1.6 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why the COP8 family offers a unique
and code-efficient instruction set - one that provides the
flexibility, functionality, reduced costs and faster time to mar-
ket that today’s microcontroller based products require.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space (ROM, OTP or Flash). Selecting a microcontroller with
less program memory size translates into lower system
costs, and the added security of knowing that more code can
be packed into the available program memory space.
1.6.1 Key Instruction Set Features
The COP8 family incorporates a unique combination of in-
struction set features, which provide designers with optimum
code efficiency and program memory utilization.
1.6.2 Single Byte/Single Cycle Code Execution
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum
program space. Because compact code does not occupy a
substantial amount of program memory space, designers
can integrate additional features and functionality into the
microcontroller program memory space. Also, the majority
instructions executed by the device are single cycle, result-
ing in minimum program execution time. In fact, 77% of the
instructions are single byte single cycle, providing greater
code and I/O efficiency, and faster code execution.
1.6.3 Many Single-Byte, Multi-Function Instructions
The COP8 instruction set utilizes many single-byte, multi-
function instructions. This enables a single instruction to
accomplish multiple functions, such as DRSZ, DCOR, JID,
LD (Load) and X (Exchange) instructions with post-
incrementing and post-decrementing, to name just a few
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