COP8SG Family, 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two
Comparators and USART
October 2001
COP8SG Family
8-Bit CMOS ROM Based and OTP Microcontrollers with
8k to 32k Memory, Two Comparators and USART
General Description
The COP8SG Family ROM and OTP based microcontrollers
are highly integrated COP8
™
Feature core devices with 8k
to 32k memory and advanced features including Analog
comparators, and zero external components. These single-
chip CMOS devices are suited for more complex applica-
tions requiring a full featured controller with larger memory,
low EMI, two comparators, and a full-duplex USART.
COP8SGx7 devices are 100% form-fit-function compatible
OTP (One Time Programmable) versions for use in produc-
tion or development of the COP8SGx5 ROM.
RAM
(bytes)
256
512
512
512
512
256
512
512
Erasable windowed versions (Q3) are available for use with
a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 15 MHz CKI with 0.67 µs instruction cycle, 14 inter-
rupts, three multi-function 16-bit timer/counters with PWM,
full duplex USART, MICROWIRE/PLUS
™
, two analog com-
parators, two power saving HALT/IDLE modes, MIWU, idle
timer, on-chip R/C oscillator, high current outputs, user se-
lectable options (WATCHDOG
™
, 4 clock/oscillator modes,
power-on-reset), 2.7V to 5.5V operation, program code se-
curity, and 28/40/44 pin packages.
Devices included in this datasheet are:
Packages
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP/SOIC, 40 DIP,
44 PLCC/QFP/CSP
28 DIP, 40 DIP, 44 PLCC
Temperature
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
-40 to +85˚C,
-40 to +125˚C
Room Temp.
Device
COP8SGE5
COP8SGG5
COP8SGH5
COP8SGK5
COP8SGR5
COP8SGE7
COP8SGR7
COP8SGR7-Q3
Memory (bytes)
8k ROM
16k ROM
20k ROM
24k ROM
32k ROM
8k OTP EPROM
32k OTP EPROM
32k EPROM
I/O Pins
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
24/36/40
Key Features
n
n
n
n
Low cost 8-bit microcontroller
Quiet Design (low radiated emissions)
Multi-Input Wakeup pins with optional interrupts (8 pins)
Mask selectable clock options
— Crystal oscillator
— Crystal oscillator option with on-chip bias resistor
— External oscillator
— Internal R/C oscillator
Internal Power-On-Reset — user selectable
WATCHDOG and Clock Monitor Logic — user selectable
Eight high current outputs
256 or 512 bytes on-board RAM
8k to 32k ROM or OTP EPROM with security feature
n
n
n
n
n
n
Fourteen multi-source vectored interrupts servicing
— External interrupt / Timers T0 — T3
— MICROWIRE/PLUS Serial Interface
— Multi-Input Wake Up
— Software Trap
— USART (2; 1 receive and 1 transmit)
— Default VIS (default interrupt)
n
8-bit Stack Pointer SP (stack in RAM)
n
Two 8-bit Register Indirect Data Memory Pointers
n
True bit manipulation
n
BCD arithmetic instructions
Peripheral Features
n
Multi-Input Wakeup Logic
n
Three 16-bit timers (T1 — T3), each with two 16-bit
registers supporting:
— Processor Independent PWM mode
— External Event Counter mode
— Input Capture mode
CPU Features
n
Versatile easy to use instruction set
n
0.67 µs instruction cycle time
COP8
™
is a trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation
DS101317
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COP8SG Family
Peripheral Features
n
n
n
n
(Continued)
Fully Static CMOS Design
n
Low current drain (typically
<
4 µA)
n
Two power saving modes: HALT and IDLE
Idle Timer (T0)
MICROWIRE/PLUS Serial Interface (SPI Compatible)
Full Duplex USART
Two Analog Comparators
Temperature Range
n
−40˚C to +85˚C, −40˚C to +125˚C
I/O Features
n
Software selectable I/O options (TRI-STATE
®
Output,Push-Pull Output, Weak Pull-Up Input, and High
Impedance Input)
n
Schmitt trigger inputs on ports G and L
n
Eight high current outputs
n
Packages: 28 SO with 24 I/O pins, 40 DIP with 36 I/O
pins, 44 PLCC, PQFP and CSP with 40 I/O pins
Development Support
n
Windowed packages for DIP and PLCC
n
Real time emulation and debug tools available
Block Diagram
10131744
FIGURE 1. COP8SGx Block Diagram
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2
COP8SG Family
1.0 Device Description
1.1 ARCHITECTURE
The COP8 family is based on a modified Harvard architec-
ture, which allows data tables to be accessed directly from
program memory. This is very important with modern
microcontroller-based applications, since program memory
is usually ROM or EPROM, while data memory is usually
RAM. Consequently data tables need to be contained in
non-volatile memory, so they are not lost when the micro-
controller is powered down. In a modified Harvard architec-
ture, instruction fetch and memory data transfers can be
overlapped with a two stage pipeline, which allows the next
instruction to be fetched from program memory while the
current instruction is being executed using data memory.
This is not possible with a Von Neumann single-address bus
architecture.
The COP8 family supports a software stack scheme that
allows the user to incorporate many subroutine calls. This
capability is important when using High Level Languages.
With a hardware stack, the user is limited to a small fixed
number of stack levels.
1.2 INSTRUCTION SET
In today’s 8-bit microcontroller application arena cost/
performance, flexibility and time to market are several of the
key issues that system designers face in attempting to build
well-engineered products that compete in the marketplace.
Many of these issues can be addressed through the manner
in which a microcontroller’s instruction set handles process-
ing tasks. And that’s why COP8 family offers a unique and
code-efficient instruction set — one that provides the flexibil-
ity, functionality, reduced costs and faster time to market that
today’s microcontroller based products require.
Code efficiency is important because it enables designers to
pack more on-chip functionality into less program memory
space. Selecting a microcontroller with less program
memory size translates into lower system costs, and the
added security of knowing that more code can be packed
into the available program memory space.
1.2.1 Key Instruction Set Features
The COP8 family incorporates a unique combination of in-
struction set features, which provide designers with optimum
code efficiency and program memory utilization.
Single Byte/Single Cycle Code Execution
The efficiency is due to the fact that the majority of instruc-
tions are of the single byte variety, resulting in minimum
program space. Because compact code does not occupy a
substantial amount of program memory space, designers
can integrate additional features and functionality into the
microcontroller program memory space. Also, the majority
instructions executed by the device are single cycle, result-
ing in minimum program execution time. In fact, 77% of the
instructions are single byte single cycle, providing greater
code and I/O efficiency, and faster code execution.
1.2.2 Many Single-Byte, Multifunction Instructions
The COP8 instruction set utilizes many single-byte, multi-
function instructions. This enables a single instruction to
accomplish multiple functions, such as DRSZ, DCOR, JID,
LD (Load) and X (Exchange) instructions with post-
incrementing and post-decrementing, to name just a few
examples. In many cases, the instruction set can simulta-
neously execute as many as three functions with the same
single-byte instruction.
JID:
(Jump Indirect); Single byte instruction; decodes exter-
nal events and jumps to corresponding service routines
(analogous to “DO CASE” statements in higher level lan-
guages).
LAID:
(Load Accumulator-Indirect); Single byte look up table
instruction provides efficient data path from the program
memory to the CPU. This instruction can be used for table
lookup and to read the entire program memory for checksum
calculations.
RETSK:
(Return Skip); Single byte instruction allows return
from subroutine and skips next instruction. Decision to
branch can be made in the subroutine itself, saving code.
AUTOINC/DEC:
(Auto-Increment/Auto-Decrement); These
instructions use the two memory pointers B and X to effi-
ciently process a block of data (analogous to “FOR NEXT” in
higher level languages).
1.2.3 Bit-Level Control
Bit-level control over many of the microcontroller’s I/O ports
provides a flexible means to ease layout concerns and save
board space. All members of the COP8 family provide the
ability to set, reset and test any individual bit in the data
memory address space, including memory-mapped I/O ports
and associated registers.
1.2.4 Register Set
Three memory-mapped pointers handle register indirect ad-
dressing and software stack pointer functions. The memory
data pointers allow the option of post-incrementing or post-
decrementing with the data movement instructions (LOAD/
EXCHANGE). And 15 memory-maped registers allow de-
signers to optimize the precise implementation of certain
specific instructions.
1.3 EMI REDUCTION
The COP8SGx5 family of devices incorporates circuitry that
guards against electromagnetic interference — an increasing
problem in today’s microcontroller board designs. National’s
patented EMI reduction technology offers low EMI clock
circuitry, gradual turn-on output drivers (GTOs) and internal
I
CC
smoothing filters, to help circumvent many of the EMI
issues influencing embedded control designs. National has
achieved 15 dB–20 dB reduction in EMI transmissions when
designs have incorporated its patented EMI reducing cir-
cuitry.
1.4 PACKAGING/PIN EFFICIENCY
Real estate and board configuration considerations demand
maximum space and pin efficiency, particularly given today’s
high integration and small product form factors. Microcon-
troller users try to avoid using large packages to get the I/O
needed. Large packages take valuable board space and
increases device cost, two trade-offs that microcontroller
designs can ill afford.
The COP8 family offers a wide range of packages and do not
waste pins: up to 90.9% (or 40 pins in the 44-pin package)
are devoted to useful I/O.
3
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COP8SG Family
Connection Diagrams
10131704
10131753
Top View
Order Number COP8SGXY28M8
See NS Package Number M28B
Order Number COP8SGXY28N8
See NS Package Number N28B
Order Number COP8SGR728Q3
See NS Package Number D28JQ
Top View
Order Number COP8SGR7HLQ8
See NS Package Number LQA44A
10131705
Top View
Order Number COP8SGXY40N8
See NS Package Number N40A
Order Number COP8SGR5740Q3
See NS Package Number D40KQ
10131706
10131743
Top View
Order Number COP8SGXY44V8
See NS Package Number V44A
Order Number COP8SGR744J3
See NS Package Number EL44C
Top View
Order Number COP8SGXYVEJ8
See NS Package Number VEJ44A
Note 1:
X = E for 8k, G for 16k,
H for 20k, K for 24k, R for 32k
Y = 5 for ROM, 7 for OTP
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4
COP8SG Family
Pinouts for 28 -, 40- and 44-Pin Packages
Port
L0
L1
L2
L3
L4
L5
L6
L7
G0
G1
G2
G3
G4
G5
G6
G7
D0
D1
D2
D3
D4
D5
D6
D7
F0
F1
F2
F3
F4
F5
F6
F7
C0
C1
C2
C3
C4
C5
C6
C7
V
CC
GND
CKI
RESET
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
23
5
24
8
33
7
34
COMP1IN−
COMP1IN+
COMP1OUT
COMP2IN−
COMP2IN+
COMP2OUT
7
8
9
10
Type
MIWU
MIWU or CKX
MIWU or TDX
MIWU or RDX
MIWU or T2A
MIWU or T2B
MIWU or T3A
MIWU or T3B
INT
WDOUT*
T1B
T1A
SO
SK
SI
CKO
Alt. Fun
28-Pin
SO
11
12
13
14
15
16
17
18
25
26
27
28
1
2
3
4
19
20
21
22
40-Pin DIP
17
18
19
20
21
22
23
24
35
36
37
38
3
4
5
6
25
26
27
28
29
30
31
32
9
10
11
12
13
14
15
16
39
40
1
2
44-Pin
PLCC
17
18
19
20
25
26
27
28
39
40
41
42
3
4
5
6
29
30
31
32
33
34
35
36
9
10
11
12
13
14
15
16
43
44
1
2
21
22
23
24
8
37
7
38
44-Pin PQFP
11
12
13
14
19
20
21
22
33
34
35
36
41
42
43
44
23
24
25
26
27
28
29
30
3
4
5
6
7
8
9
10
37
38
39
40
15
16
17
18
2
31
1
32
44-Pin CSP
12
13
14
15
20
21
22
23
34
35
36
37
42
43
44
1
24
25
26
27
28
29
30
31
4
5
6
7
8
9
10
11
38
39
40
41
16
17
18
19
3
32
2
33
* G1 operation as WDOUT is controlled by ECON bit 2.
5
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