CP3BT26 Connectivity Processor with Bluetooth and Dual CAN Interfaces
FINAL
JULY 2004
CP3BT26 Reprogrammable Connectivity Processor with
Bluetooth
®
, USB, and CAN Interfaces
1.0
General Description
advanced power-saving modes achieve new design points
in the trade-off between battery size and operating time for
handheld and portable applications.
The CP3BT26 connectivity processor combines high perfor-
mance with the massive integration needed for embedded
Bluetooth applications. A powerful RISC core with on-chip
SRAM and Flash memory provides high computing band-
width, hardware communications peripherals provide high-
I/O bandwidth, and an external bus provides system ex-
pandability.
In addition to providing the features needed for the next gen-
eration of embedded Bluetooth products, the CP3BT26 is
backed up by the software resources designers need for
rapid time-to-market, including an operating system, Blue-
On-chip communications peripherals include: Bluetooth tooth protocol stack implementation, peripheral drivers, ref-
Lower Link Controller, Universal Serial Bus (USB) 1.1 node, erence designs, and an integrated development
CAN, Microwire/Plus, SPI, ACCESS.bus, quad UART, 12-bit environment. Combined with a Bluetooth radio transceiver
A/D converter, and Advanced Audio Interface (AAI). Addi- such as National’s LMX5252, the CP3BT26 provides a com-
tional on-chip peripherals include Random Number Gener- plete Bluetooth system solution.
ator (RNG), DMA controller, CVSD/PCM conversion National Semiconductor offers a complete and industry-
module, Timing and Watchdog Unit, Versatile Timer Unit, proven application development environment for CP3BT26
Multi-Function Timer, and Multi-Input Wake-Up (MIWU) applications, including the IAR Embedded Workbench,
unit.
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Bluetooth hand-held devices can be both smaller and lower Development Board, Bluetooth Protocol Stack, and Applica-
in cost for maximum consumer appeal. The low voltage and tion Software.
Block Diagram
Clock Generator
12 MHz and 32 kHz
Oscillator
PLL and Clock
Generator
Power-on-Reset
Bluetooth Lower
Link Controller
CR16C
CPU Core
256K Bytes
Flash
Program
Memory
8K Bytes
Flash
Data
32K Bytes
Static
RAM
RF Interface
CAN 2.0B
Controller
Protocol
Core
1K Byte
Sequencer RAM
4.5K Bytes
Data RAM
Serial
Debug
Interface
CPU Core Bus
Bus
Interface
Unit
DMA
Controller
Peripheral
Bus
Controller
Interrupt
Control
Unit
CVSD/PCM
Converter
Power
Manage-
ment
Timing and
Watchdog
Unit
Random
Number
Generator
Peripheral Bus
GPIO
Audio
Interface
Microwiire/
SPI
Quad UART
ACCESS
.bus
Versatile
Timer Unit
Muti-Func-
tion Timer
Multi-Input
Wake-Up
8-Channel
12-bit ADC
USB
DS202
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2004 National Semiconductor Corporation
www.national.com
CP3BT26
Table of Contents
1.0
2.0
3.0
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
CR16C CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit (ICU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth LLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD/PCM Conversion Module. . . . . . . . . . . . . . . . . . . . . . . . . . .
12-bit Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . .
Random Number Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Function Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
4
4
4
4
5
5
5
5
5
5
5
6
6
6
6
6
6
6
7
7
7
7
16.3
16.4
16.5
ADC Operation in Power-Saving Modes . . . . . . . . . . . . . . . . . . . 83
Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Random Number Generator Register Set . . . . . . . . . . . . . . . . . . 89
Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Endpoint Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
USB Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic CAN Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Message Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Stamp Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Start-Up and Multi-Input Wake-Up. . . . . . . . . . . . . . . . .
Usage Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communication Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM to CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD to PCM Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Freeze. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Interface Registers . . . . . . . . . . . . . . . . . . . . . . . .
Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TWM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer T0 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Programming Procedure . . . . . . . . . . . . . . . . . . . . . .
Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
110
118
119
120
123
125
126
127
128
140
142
143
143
146
146
146
148
151
158
158
159
159
159
159
159
160
160
163
163
168
172
175
177
178
178
179
181
183
185
189
192
192
193
193
195
196
197
202
202
203
17.0
18.0
Random Number Generator (RNG). . . . . . . . . . . . . . 88
17.1
17.2
18.1
18.2
18.3
18.4
USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.0
CAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
19.10
19.11
19.12
20.0
Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . 143
20.1
20.2
20.3
20.4
20.5
20.6
20.7
4.0
5.0
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dedicated Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Status Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register (CFG). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
17
18
19
19
24
25
25
25
28
21.0
CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 158
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
6.0
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
6.2
6.3
6.4
6.5
7.0
System Configuration Registers . . . . . . . . . . . . . . . 29
7.1
7.2
7.3
Module Configuration Register (MCFG) . . . . . . . . . . . . . . . . . . . . 29
Module Status Register (MSTAT). . . . . . . . . . . . . . . . . . . . . . . . . 30
Software Reset Register (SWRESET) . . . . . . . . . . . . . . . . . . . . . 30
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Block Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . .
Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Between Power Modes . . . . . . . . . . . . . . . . . . . . . . . .
31
31
32
34
35
41
41
42
43
43
43
47
47
47
50
50
52
53
53
53
54
54
54
54
54
56
56
57
57
57
57
59
22.0
UART Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
22.1
22.2
22.3
22.4
8.0
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1
8.2
8.3
8.4
8.5
23.0
Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 175
23.1
23.2
23.3
23.4
23.5
9.0
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
9.2
9.3
9.4
9.5
9.6
24.0
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 181
24.1
24.2
24.3
24.4
10.0
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1
10.2
10.3
10.4
10.5
25.0
Timing and Watchdog Module . . . . . . . . . . . . . . . . 192
25.1
25.2
25.3
25.4
25.5
11.0
Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 51
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
26.0
Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 196
26.1
26.2
26.3
26.4
26.5
27.0
28.0
29.0
30.0
Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 206
27.1
27.2
VTU Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.0
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 243
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
30.9
30.10
30.11
30.12
30.13
30.14
30.15
30.16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Transceiver Electrical Characteristics . . . . . . . . . . . . . . . .
ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory On-Chip Programming . . . . . . . . . . . . . . . . . . . .
Output Signal Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Audio Interface (AAI) Timing . . . . . . . . . . . . . . . . . . .
Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . . . . . . . .
Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . . . . . . . .
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
243
243
245
245
246
247
247
249
250
251
253
258
261
261
262
263
13.0
14.0
15.0
Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.1
13.2
14.1
14.2
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Multi-Input Wake-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMX5251 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .
LMX5252 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth Global Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth Sequencer RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bluetooth Shared Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
73
76
76
77
77
77
78
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bluetooth Controller . . . . . . . . . . . . . . . . . . . . . . . . . 72
31.0
32.0
33.0
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
31.1
31.2
LQFP-128 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
LQFP-144 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
16.0
12-Bit Analog to Digital Converter . . . . . . . . . . . . . . 79
16.1
16.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Touchscreen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 277
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2
CP3BT26
2.0
Features
Power-down modes
Flexible I/O
Up to 54 general-purpose I/O pins (shared with on-chip
peripheral I/O)
Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-imped-
ance input
Schmitt triggers on general-purpose inputs
Multi-Input Wake-Up (MIWU) capability
Power Supply
I/O port operation at 2.5V to 3.3V
Core logic operation at 2.5V
On-chip power-on reset
CPU Features
Fully static RISC processor core, capable of operating
from 0 to 24 MHz with zero wait/hold states
Minimum 41.7 ns instruction cycle time with a 24-MHz in-
ternal clock frequency, based on a 12-MHz external input
47 independently vectored peripheral interrupts
On-Chip Memory
256K bytes reprogrammable Flash program memory
8K bytes Flash data memory
32K bytes of static RAM data memory
Addresses up to 12M bytes of external memory
Broad Range of Hardware Communications Peripherals
Temperature Range
Bluetooth Lower Link Controller (LLC) including a shared
-40°C to +85°C (Industrial)
4.5K byte Bluetooth RAM and 1K byte Bluetooth Se-
quencer RAM
Packages
Universal Serial Bus (USB) 1.1 full-speed node
LQFP-128, LQFP-144
ACCESS.bus serial bus (compatible with Philips I
2
C bus)
CAN interface with 15 message buffers conforming to
Complete Development Environment
CAN specification 2.0B active
Pre-integrated hardware and software support for rapid
8/16-bit SPI, Microwire/Plus serial interface
prototyping and production
Four-channel Universal Asynchronous Receiver/Trans-
Integrated environment
mitter (UART), one channel has USART capability
Project manager
Advanced Audio Interface (AAI) to connect to external 8/
Multi-file C source editor
13-bit PCM Codecs as well as to ISDN-Controllers
High-level C source debugger
through the IOM-2 interface (slave only)
Comprehensive, integrated, one-stop technical support
CVSD/PCM converter supporting one bidirectional audio
Bluetooth Protocol Stack
connection
Applications can interface to the high-level protocols or
General-Purpose Hardware Peripherals
directly to the low-level Host Controller Interface (HCI)
12-bit A/D Converter (ADC)
Transport layer support allows HCI command-based in-
Dual 16-bit Multi-Function Timer (MFT)
terface over UART port
Versatile Timer Unit with four subsystems (VTU)
Baseband (Link Controller) hardware minimizes the
Four-channel DMA controller
bandwidth demand on the CPU
Timing and Watchdog Unit
Link Manager (LM)
Random Number Generator peripheral
Logical Link Control and Adaptation Protocol (L2CAP)
Service Discovery Protocol (SDP)
Extensive Power and Clock Management Support
RFCOMM Serial Port Emulation Protocol
On-chip Phase Locked Loop
All packet types, piconet, and scatternet functionality
Support for multiple clock options
supported
Dual clock and reset
CP3BT26 Connectivity Processor Selection Guide
NSID
CP3BT26G18NEP
CP3BT26G18NEPNOPB
CP3BT26G18NEPX
CP3BT26G18NEPXNOPB
CP3BT26Y98NEP
CP3BT26Y98NEPNOPB
CP3BT26Y98NEPX
CP3BT26Y98NEPXNOPB
Speed
Temp. Range
(MHz)
24
24
24
24
24
24
24
24
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
Program
Flash
(Kbytes)
256
256
256
256
256
256
256
256
Data
Flash
(Kbytes)
8
8
8
8
8
8
8
8
SRAM
(Kbytes)
32
32
32
32
32
32
32
32
External
Address
Lines
0
0
0
0
23
23
23
23
I/Os
54
54
54
54
48
48
48
48
Package
Type
LQFP-128
LQFP-128
LQFP-128
LQFP-128
LQFP-144
LQFP-144
LQFP-144
LQFP-144
NEP - Erased part (Bluetooth device address in Information Block 1); X - Tape and reel; NOPB - No lead solder
3
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CP3BT26
3.0
Device Overview
3.3
INPUT/OUTPUT PORTS
The device has up to 54 software-configurable I/O pins, or-
ganized into seven ports called Port B, Port C, Port E, Port
G, Port H, Port I, and Port J. Each pin can be configured to
operate as a general-purpose input or general-purpose out-
put. In addition, many I/O pins can be configured to operate
as inputs or outputs for on-chip peripheral modules such as
the UART, timers, or Microwire/SPI interface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
The CP3BT26 connectivity processor is a complete micro-
computer with all system timing, interrupt logic, program
memory, data memory, and I/O ports included on-chip, mak-
ing it well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip com-
ponents of the CP3BT26 devices.
3.1
CR16C CPU CORE
The CP3BT26 device implements the CR16C CPU core
module. The high performance of the CPU core results from
the implementation of a pipelined architecture with a two-
bytes-per-cycle pipelined system bus. As a result, the CPU
can support a peak execution rate of one instruction per
clock cycle.
For more information, please refer to the CR16C Program-
mer’s Reference Manual (document number 424521772-
101, which may be downloaded from National’s web site at
http://www.national.com).
3.4
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls access to internal/ex-
ternal memory and I/O. It determines the configured param-
eters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are used when accessing
Flash program memory and the I/O area. At start-up, the
configuration registers are set for slowest possible memory
access. To achieve fastest possible program execution, ap-
propriate values must be programmed. These settings vary
with the clock frequency and the type of off-chip device be-
ing accessed.
3.2
MEMORY
The CP3BT26 devices support a uniform linear address
space of up to 16 megabytes. Three types of on-chip mem-
ory occupy specific regions within this address space, along
with any external memory:
256K bytes of Flash program memory
8K bytes of Flash data memory
32K bytes of static RAM
Up to 12M bytes of external memory (144-pin devices)
The 256K bytes of Flash program memory are used to store
the application program, Bluetooth protocol stack, and real-
time operating system. The Flash memory has security fea-
tures to prevent unintentional programming and to prevent
unauthorized access to the program code. This memory
can be programmed with an external programming unit or
with the device installed in the application system (in-sys-
tem programming).
3.5
INTERRUPT CONTROL UNIT (ICU)
The ICU receives interrupt requests from internal and exter-
nal sources and generates interrupts to the CPU. An inter-
rupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execu-
tion continues with the next instruction in the program fol-
lowing the point of interruption.
Interrupts from the timers, UARTs, Microwire/SPI interface,
The 8K bytes of Flash data memory are used for non-vola- and Multi-Input Wake-Up, are all maskable interrupts; they
tile storage of data entered by the end-user, such as config- can be enabled or disabled by software. There are 47
uration settings.
maskable interrupts, assigned to 47 linear priority levels.
The 32K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, de-
pending on the instruction executed by the CPU.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI
input pin.
Up to 12M bytes of external memory can be added on an
external bus. The external bus is only available on devices The two Multi-Input Wake-Up (MIWU) modules can be used
for two purposes: to provide inputs for waking up (exiting)
in 144-pin packages.
from the Halt, Idle, or Power Save mode, and to provide gen-
For Flash program and data memory, the device internally eral-purpose edge-triggered maskable interrupts to the lev-
generates the necessary voltages for programming. No ad- el-sensitive interrupt control unit (ICU) inputs. Each 16-
ditional power supply is required.
channel module generates four programmable interrupts to
the ICU, for a total of 8 ICU inputs generated from 32 MIWU
inputs. Channels can be individually enabled or disabled,
and programmed to respond to positive or negative edges.
3.6
MULTI-INPUT WAKE-UP
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4
CP3BT26
3.7
BLUETOOTH LLC
3.11
ADVANCED AUDIO INTERFACE
The integrated hardware Bluetooth Lower Link Controller The audio interface provides a serial synchronous, full-du-
(LLC) complies to the Bluetooth Specification Version 1.1 plex interface to CODECs and similar serial devices. Trans-
and integrates the following functions:
mit and receive paths operate asynchronously with respect
to each other. Each path uses three signals for communica-
4.5K-byte dedicated Bluetooth Data RAM
tion: shift clock, frame synchronization, and data.
1K-byte dedicated Bluetooth Sequencer RAM
Support of all Bluetooth 1.1 packet types
Support for fast frequency hopping of 1600 hops/s
Access code correlation and slot timing recovery circuit
Power Management Control Logic
BlueRF-compatible interface (mode 2/3) to connect with
National’s LMX5252 and other RF transceiver chips
When the receiver and transmitter use separate shift clocks
and frame sync signals, the interface operates in its asyn-
chronous mode. Alternatively, the transmit and receive path
can share the same shift clock and frame sync signals for
synchronous mode operation.
3.12
CVSD/PCM CONVERSION MODULE
3.8
The CVSD/PCM module performs conversion between
The CR16 USB node is a Universal Serial Bus (USB) Node CVSD data and PCM data, in which the CVSD encoding is
controller compatible with USB Specification 1.1. It inte- as defined in the Bluetooth specification and the PCM data
grates the required USB transceiver, the Serial Interface En- can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.
gine (SIE), and USB endpoint FIFOs. A total of seven
12-BIT ANALOG TO DIGITAL
endpoint pipes are supported: one bidirectional pipe for the
3.13
CONVERTER
mandatory control EP0 and an additional six pipes for unidi-
rectional endpoints to support USB interrupt, bulk, and iso- This device contains an 8-channel, multiplexed input, suc-
chronous data transfers.
cessive approximation, 12-bit Analog-to-Digital Converter. It
supports both Single Ended and Differential modes of oper-
3.9
CAN INTERFACE
ation.
The CAN module contains a Full CAN 2.0B class, CAN se-
The integrated 12-bit ADC provides the following features:
rial bus interface for applications that require a high-speed
8-channel, multiplexed input
(up to 1 Mbits per second) or a low-speed interface with
4 differential channels
CAN bus master capability. The data transfer between CAN
Single-ended and differential external filtering capability
and the CPU is established by 15 memory-mapped mes-
12-bit resolution; 11-bit accuracy
sage buffers, which can be individually configured as re-
15-microsecond conversion time
ceive or transmit buffers. An incoming message is filtered by
Support for 4-wire touchscreen applications
two masks, one for the first 14 message buffers and another
External start trigger
one for the 15th message buffer to provide a basic CAN
Programmable start delay after start trigger
path. A priority decoder allows any buffer to have the high-
Poll or interrupt on done
est or lowest transmit priority. Remote transmission re-
quests can be processed automatically by automatic The ADC is compatible with 4-wire resistive touchscreen
reconfiguration to a receiver after transmission or by auto- applications and is intended to provide the resolution neces-
mated transmit scheduling upon reception. In addition, a sary to support handwriting recognition. Low-ohmic touch-
time stamp counter (16-bits wide) is provided to support screen drivers are provided internally on the ADC[3:0] pins.
real-time applications.
Pendown detection is also provided.
The CAN module is a fast core bus peripheral, which allows The ADC provides several options for the voltage reference
single-cycle byte or word read/write access. A set of diag- source. The positive reference can be ADVCC (internal),
nostic features (such as loopback, listen only, and error VREFP, ADC0, or ADC3. The negative reference can be
identification) support the development with the CAN mod- ADVCC (internal), ADC1, or ADC2.
ule and provide a sophisticated error management tool.
Two specific analog channel selection modes are support-
The CAN receiver can trigger a wake-up condition out of the ed. These are as follows:
low-power modes through the Multi-Input Wake-Up module.
Allow any specific channel to be selected at one time.
The A/D Converter performs the specific conversion re-
3.10
QUAD UART
quested and stops.
Four UART modules support a wide range of programmable
Allow any differential channel pair to be selected at one
baud rates and data formats, parity generation, and several
time. The A/D Converter performs the specific differential
error detection schemes. The baud rate is generated on-
conversion requested and stops.
chip, under software control. One UART channel supports
hardware flow control, DMA, and USART capability (syn- In both Single-Ended and Differential modes, there is the
capability to connect the analog multiplexer output and A/D
chronous mode).
converter input to external pins. This provides the ability to
The UARTs offer a wake-up condition from the low-power
externally connect a common filter/signal conditioning cir-
modes using the Multi-Input Wake-Up module.
cuit for the A/D Converter.
USB
5
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