DATASHEET
82C55A
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
FN2969
Rev 11.00
Dec 8, 2015
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10A
Ordering Information
PART NUMBERS
5MHz
CP82C55A-5
(No longer available,
recommended
replacement:
CP82C55A-5Z)
CP82C55A-5Z (Note)
PART
MARKING
CP82C55A-5
8MHz
CP82C55A
PART
MARKING
CP82C55A
TEMP.
RANGE (°C)
0 to +70
PACKAGE
40 Ld PDIP
PKG. DWG. #
E40.6
CP82C55A-5Z CP82C55AZ (Note)
IP82C55A
IP82C55AZ (Note)
CP82C55AZ
IP82C55A
IP82C55AZ
CS82C55A*
0 to +70
-40 to +85
-40 to +85
0 to +70
40 Ld PDIP (Pb-free)
40 Ld PDIP
40 Ld PDIP (Pb-free)
44 Ld PLCC
N44.65
CS82C55A-5*
(No longer available,
recommended
replacement:
CS82C55A-5Z)
CS82C55A-5Z* (Note)
IS82C55A-5*
IS82C55A-5Z* (Note)
CS82C55A-5
CS82C55A*
CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ
IS82C55A-5
IS82C55A-5Z
IS82C55A*
IS82C55AZ* (Note)
CQ82C55AZ (Note)
IQ82C55AZ* (Note)
ID82C55A
MD82C55A/B
8406602QA
8406602XA
IS82C55A*
IS82C55AZ
CQ82C55AZ
IQ82C55AZ
ID82C55A
MD82C55A/B
8406602QA
8406602XA
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
-55 to +125
SMD#
SMD#
44 Ld PLCC (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld MQFP (Pb-free)
44 Ld MQFP (Pb-free)
40 Ld CERDIP
F40.6
Q44.10x10
44 Ld CLCC
J44.A
*Add “96” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2969 Rev 11.00
Dec 8, 2015
Page 1 of 30
82C55A
Pinouts
82C55A (PDIP, CERDIP)
TOP VIEW
PA0
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
PB6
PB5
PB4
PB3
RD
CS
82C55A (CLCC)
TOP VIEW
PA1
PA2
PA3
PA4
PA5
PA6
PA7
V
CC
WR
39 NC
38 RESET
37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6
30 D7
29 NC
18 19 20 21 22 23 24 25 26 27 28
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
WR
6 5 4 3
GND
NC
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
7
8
9
10
11
12
13
14
15
16
17
2 1 44 43 42 41 40
82C55A (PLCC)
TOP VIEW
RD
PA0
PA1
PA2
PA3
NC
PA4
PA5
PA6
PA7
WR
PA0
PA1
RD
82C55A (MQFP)
TOP VIEW
PA2
PA3
PA4
PA5
PA6
PA7
NC
6 5 4 3 2 1 44 43 42 41 40
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
7
8
9
10
11
12
13
14
15
16
17
18 1920 21 22 23 24 25 26 27 28
PC2
PC3
PB0
PB1
PB2
NC
PB3
PB4
PB5
PB6
PB7
39
38
37
36
35
34
33
32
31
30
29
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
V
CC
44 43 42 41 40 39 38 37 36 35 34
33
2
32
3
4
5
6
7
8
9
10
31
30
29
28
27
26
25
24
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
1
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
11
23
12 13 14 15 16 17 18 19 20 21 22
PB0
PB1
PB2
PB4
PB5
PC3
PB3
PB6
NC
NC
FN2969 Rev 11.00
Dec 8, 2015
NC
Page 2 of 30
82C55A
Pin Description
SYMBOL
V
CC
GND
D0-D7
RESET
CS
RD
WR
A0-A1
I/O
I
I
I
I
I
TYPE
DESCRIPTION
V
CC
: The +5V power supply pin. A 0.1F capacitor between V
CC
and GND is recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus
Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
PA0-PA7
PB0-PB7
PC0-PC7
I/O
I/O
I/O
Functional Diagram
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7-PA0
BIDIRECTIONAL
DATA BUS
D7-D0
DATA BUS
BUFFER
8-BIT
INTERNAL
DATA BUS
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
I/O
PC7-PC4
I/O
PC3-PC0
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-PB0
CS
FN2969 Rev 11.00
Dec 8, 2015
Page 3 of 30
82C55A
Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface the
82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7-
PA0
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.
(CS)
Chip Select. A “low” on this input pin enables the
communication between the 82C55A and the CPU.
(RD)
Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR)
Write. A “low” on this input pin enables the CPU to write
data or control words into the 82C55A.
(A0 and A1)
Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word register.
They are normally connected to the least significant bits of the
address bus (A0 and A1).
82C55A BASIC OPERATION
A1
0
0
1
1
A0
0
1
0
1
RD
0
0
0
0
WR
1
1
1
1
CS
0
0
0
0
INPUT OPERATION
(READ)
Port A
Data
Bus
Port B
Data
Bus
Port C
Data
Bus
Control Word
Data
Bus
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus
Port
A
Data Bus
Port
B
Data Bus
Port
C
Data Bus
Control
DISABLE FUNCTION
X
X
X
X
X
1
X
1
1
0
Data Bus
Three-State
Data Bus
Three-State
BIDIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER
GROUP A
PORT C
UPPER
(4)
8-BIT
INTERNAL
DATA BUS
GROUP B
CONTROL
GROUP B
PORT C
LOWER
(4)
I/O
PC7-
PC4
I/O
PC3-
PC0
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
PORT B
(8)
I/O
PB7-
PB0
CS
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
Group A and Group B Controls
The functional configuration of each port is programmed by the
systems software. In essence, the CPU “outputs” a control
word to the 82C55A. The control word contains information
such as “mode”, “bit set”, “bit reset”, etc., that initializes the
functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations. When
the control word is read, bit D7 will always be a logic “1”, as this
implies control word mode information.
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can be
configured to a wide variety of functional characteristics by the
system software but each has its own special features or
“personality” to further enhance the power and flexibility of the
82C55A.
Port A
One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices are
present on Port A. See Figure 2A.
Port B
One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C
One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
(RESET)
Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input mode.
“Bus hold” devices internal to the 82C55A will hold the I/O port
inputs to a logic “1” state with a maximum hold current of
400A.
FN2969 Rev 11.00
Dec 8, 2015
Page 4 of 30
82C55A
two 4-bit ports under the mode control. Each 4-bit port contains
a 4-bit latch and it can be used for the control signal output and
status signal inputs in conjunction with ports A and B. See
Figure 2B.
INPUT MODE
RD, WR
EXTERNAL
PORT A PIN
D7-D0
82C55A
MODE 0
B
8
OUTPUT MODE
I/O
4
C
A0-A1
CS
A
4
I/O
8
I/O
ADDRESS BUS
CONTROL BUS
DATA BUS
MASTER
RESET
OR MODE
CHANGE
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
I/O
PB7-PB0
MODE 1
B
8
I/O
PC3-PC0
C
PC7-PC4
PA7-PA0
A
8
I/O
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
RESET
OR MODE
CHANGE
V
CC
P
PB7-PB0
MODE 2
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
OUTPUT MODE
EXTERNAL
PORT B, C
PIN
CONTROL CONTROL
OR I/O
OR I/O
C
PA7-PA0
B
8
I/O
A
BI-
DIRECTIONAL
PB7-PB0
CONTROL
PA7-PA0
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
Operational Description
Mode Selection
There are three basic modes of operation than can be selected
by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional
initialization required. This eliminates the need to pull-up or
pull-down resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output port
is initialized to all zeros when the control word is written.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
FN2969 Rev 11.00
Dec 8, 2015
Page 5 of 30
