High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1.
2.
3.
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Ultra low power consumption :
2.0V (min) data retention
Low operation voltage : 4.5 ~ 5.5V ; 5mA＠1MHz (Max.) operating current (Vcc = 5.0V)
4.
5.
Standby Typ. =
0.50uA, (Typical value @ Vcc = 5.0V, TA = 25
0
C)
Standard pin configuration
32 - SOP 450mil
32 - sTSOP-I - 8X13.4mm
32 - TSOP-I
8X20mm
32 - PDIP 600mil
Product Family
Part No.
CS18LV10245CC
CS18LV10245DC
CS18LV10245EC
CS18LV10245LC
CS18LV10245CI
CS18LV10245DI
CS18LV10245EI
CS18LV10245LI
Note: Green package part no, sees order information.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
.
Rev. 1.2
P1
-40~85
o
C
0~70 C
o
Operating Temp Vcc. Range Speed (ns)
Standby (Typ.)
Package Type
32 SOP
0.50uA
32 STSOP
32 TSOP (I)
4.5 ~ 5.5
55/70
0.80uA
32 PDIP
32 SOP
32 STSOP
32 TSOP (I)
32 PDIP
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
PIN CONFIGURATIONS
32 SOP 450 mil
32 PDIP 600 mil
32 STSOP 8x13.4mm
32 TSOP(I) 8x20mm
BLOCK DIAGRAM
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
.
Rev. 1.2
P2
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Function
PIN DESCRIPTIONS
Name
A0-A16
Address Input
/CE
Chip Enable Input
CE2
Chip Enable 2 Input
/WE
Write Enable Input
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active,
the device is deselected and is in a standby power mode. The DQ pins will be
in the high impedance state when the device is deselected.
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Output Enable Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0-DQ7
Data Input/Output
Ports
Vcc
Gnd
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not
Selected
Output
Disabled
Read
Write
/WE
X
X
H
H
L
/CE
H
X
L
L
L
CE2
X
L
H
H
H
/OE
X
X
H
L
X
DQ0~7
High Z
High Z
D
OUT
D
IN
Vcc Current
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
.
Rev. 1.2
P3
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
20
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Unit
V
O
O
C
C
W
mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0~70
o
C
-40~85
o
C
Vcc
4.5V ~5.5V
4.5V ~ 5.5V
CAPACITANCE
(1)
(TA = 25
o
C, f =1.0 MHz)
Symbol
C
IN
C
DQ
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
=0V
V
I/O
=0V
MAX.
6
8
Unit
pF
pF
1.
This parameter is guaranteed and not tested.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
.
Rev. 1.2
P4
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
( TA = 0 to + 70 C )
o
DC ELECTRICAL CHARACTERISTICS
Parameter
Name
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
Parameter
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current V
CC
=MAX, V
IN
=0 to V
CC
Output Leakage
Current
Output Low Voltage
V
CC
=MAX, /CE=V
IN
, or
/OE=V
IN
, V
IO
=0V to V
CC
V
CC
=MAX, I
OL
= 2mA
V
CC
=MIN, I
OH
= -1mA
Test Conduction
MIN
-0.5
TYP
(1)
MAX
0.8
Unit
V
2.0
Vcc+0.2
V
1
1
uA
uA
0.4
V
Output High Voltage
Operating Power
Supply Current
Standby Supply - TTL
Standby Current
-CMOS
2.4
35
V
mA
/CE=V
IL
, I
DQ
=0mA, F=F
MAX(3)
/CE=V
IH
, I
DQ
=0mA,
/CE≧V
CC
-0.2V, V
IN
≧
V
CC
-0.2V or V
IN
≦0.2V
o
2
0.3
10
mA
uA
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3.
Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0 to +70
o
C )
Parameter
Name
V
RD
I
CCDR
T
CDR
t
R
Parameter
V
CC
for Data Retention
Data Retention Current
Test Conduction
/CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
/CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN
1.5
TYP
(1)
MAX Unit
V
0.2
2.0
uA
Chip Deselect to Data
Retention Time
Operation Recovery Time
o
See Retention Waveform
0
t
RC (2)
ns
ns
1. Vcc = 3.0V, TA = + 25 C. 2. t
RC
= Read Cycle Time.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
.
Rev. 1.2
P5
