Low Power Pseudo SRAM
2 M word x 16 bit
CS26LV32163
Description
The CS26LV32163 is a high performance, high speed, low power pseudo SRAM
organized as 2,097,152 words by 16 bits and operates from a wide range of 2.7 to 3.3V
supply voltage. Advanced DRAM technology and circuit techniques provide both high speed
and low power features with a typical standby current of 8uA and maximum access time of
70/85ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip
enable (/CE) and active LOW output enable (/OE) and three-state output drivers.
The CS26LV32163 has an automatic power down feature, reducing the power
consumption significantly when chip is deselected. The CS26LV32163 is available 48-pin
BGA package.
The efficient Page Read Mode, data can be read by only changing A0-A2 when A3-A20
is fixed while /CE1=L, /WE=H, /OE=L, /UB=L, /LB=L.
Features
Low operation voltage : 2.7 ~ 3.3V
Ultra low power consumption :
Vcc = 3.0V
5mA＠1MHz (Max.) operating current
8uA (Typ.) CMOS standby current
High speed access time : 70~85ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible,
Asynchronous SRAM compatible operation
Easy expansion with /CE and /OE options.
Product Family
Part No.
CS26LV32163ZC
CS26LV32163HC
CS26LV32163ZI
CS26LV32163HI
Operating
Vcc. Range
Temp
0~70
o
C
-40~85 C
o
Speed (ns)
70/85
70/85
Standby
(Typ.)
8uA
(Vcc = 3.0V)
8uA
(Vcc = 3.0V)
Package Type
Dice
48 CSP-0608
Dice
48 CSP-0608
2.7~3.3
2.7~3.3
Note: Green package part no, see order information.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.1
P1
Low Power Pseudo SRAM
2 M word x 16 bit
CS26LV32163
Pin Configuration
1
2
3
4
5
6
A
/LB
/OE
A0
A1
A2
CE2
B
I/O8
/UB
A3
A4
/CE1
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
VSS
I/O11
A17
A7
I/O3
VCC
E
VCC
I/O12
NC
A16
I/O4
VSS
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
A19
A12
A13
/WE
I/O7
H
A18
A8
A9
A10
A11
A20
48 Ball CSP - Top View
Functional Block Diagram
A0
Row
Address
Input
Buffer
A20
CE1
WE
OE
UB
LB
CE2
Column
Decoder
Decoder
2M x 16
Memory Array
Control
I/O buffer
I/O0
I/O15
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.1
P2
Low Power Pseudo SRAM
2 M word x 16 bit
CS26LV32163
Function
Pin Description
Name
A0-A20 Address Input
/CE1 &CE2 Chip
Enable Input
A0~A2, page address inputs, while A3~A20 address inputs
/CE is active LOW. Chip enables must be active when data read from
or write to the device. if chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the
high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is
LOW, output data will be present on the DQ pins; when /WE is LOW,
the data present on the DQ pins will be written into the selected
memory location.
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be
in the high impedance state when /OE is inactive.
/WE Write Enable
Input
/OE Output Enable
Input
/LB and /UB Data Byte
Lower byte and upper byte data input/output control pins.
Control Input
I/O0-I/O15 Data
Input/Output Ports
Vcc
Vss
These 16 bi-directional ports are used to read data from or write data
into the RAM.
Power Supply
Ground
Truth Table
MODE
Power Down
(No data retention)
Not Selected
Output Disabled
Read
L
Write
L
X
H
/CE1 CE2 /WE /OE
L
H
L
X
X
X
H
H
X
X
X
H
L
/LB
H
X
X
X
L
H
L
L
H
L
/UB
H
X
X
X
L
L
H
L
L
H
IO0~7
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
IO8~15
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
Vcc Current
I
CCSB2
I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.1
P3
Low Power Pseudo SRAM
2 M word x 16 bit
CS26LV32163
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
20
Unit
V
O
Absolute Maximum Ratings
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
O
W
mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
( TA = 0 to + 70
o
C , Vcc = 3.0V )
Parameter
Name
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
I
CCSB2
Parameter
Input Low Voltage
(2)
Input High Voltage
(2)
Input Leakage Current
V
CC
=MAX, V
IN
=0 to V
CC
Output Leakage Current V
CC
=MAX, /CE=V
IN
, or
/OE=V
IN
, V
IO
=0V to V
CC
Output Low Voltage
Output High Voltage
V
CC
=MAX, I
OL
= 2mA
2.4
18
1
5
70
25
V
CC
=MIN, I
OH
= -1mA
Operating Power Supply /CE1≦V
IL
, CE2≧V
IH
Current
I
DQ
=0mA, F=F
MAX(3)
/CE1&CE2≧V
IH
,
Standby Supply - TTL
I
DQ
=0mA,
Standby Current -CMOS /CE≧V
CC
-0.2V, V
IN
≧
V
CC
-0.2V or V
IN
≦0.2V
Standby Current –CMOS /CE≧V
CC
-0.2V, V
IN
≧
(power down mode, no V
CC
-0.2V or V
IN
≦0.2V
data retention)
Test Conduction
MIN TYP
(1)
-0.5
2.0
-1
-1
MAX Unit
0.8
1
1
0.4
V
uA
uA
V
V
mA
mA
uA
uA
Vcc+0.2
V
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.1
P4
Low Power Pseudo SRAM
2 M word x 16 bit
o
CS26LV32163
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3.
Fmax = 1/t
RC
.
Capacitance
(1)
(TA = 25
o
C, f =1.0 MHz)
Symbol
C
IN
C
DQ
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
=0V
V
I/O
=0V
MAX.
10
10
Unit
pF
pF
1. This parameter is guaranteed and not tested.
AC Test Conditions
Input Pulse Levels
Input and Output
Timing Reference Level
0.5Vcc
Vcc/0V
Input Rise and Fall Times 5ns
Key To Switching Waveforms
Waveform
Inputs
Must be standby
May change for H to L
May change for L to H
Don’t care any change permitted
Does not apply
Outputs
Must be standby
Will be change from H to L
May change for L to H
Change state unknown
Center line is high impedance
“OFF” state
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.1
P5
