CS4327
Low Cost, 20-Bit, Stereo, Audio D/A Converter
Features
Description
The CS4327 is a complete stereo digital-to-analog out-
put system. In addition to the traditional D/A function, the
CS4327 includes a digital interpolation filter followed by
an 128X oversampled delta-sigma modulator. The mod-
ulator output controls the reference voltage input to an
ultra-linear analog low-pass filter. This architecture al-
lows for infinite adjustment of sample rate between 1 and
50 kHz while maintaining linear phase response simply
by changing the master clock frequency.
The CS4327 also includes an extremely flexible serial
port utilizing mode select pins to support multiple inter-
face formats.
The master clock can be either 256, 384, or 512 times
the input sample rate, supporting various audio
environments.
ORDERING INFO
CS4327-KS -10 to 70 °C
16-pin Plastic SSOP
CDB4327
CS4327 Evaluation Board
l
20-Bit Conversion
l
108 dB Signal-to-Noise-Ratio (EIAJ)
l
100 dB Dynamic Range
l
Single-Ended Outputs
l
Complete Stereo DAC System
-
128X Interpolation Filter
-
Delta-Sigma DAC
-
Analog Post Filter
l
Low Clock Jitter Sensitivity
l
Filtered Line-Level Outputs
l
Digital De-emphasis for 32 kHz, 44.1 kHz &
48 kHz
-
Linear Phase Filtering
-
Zero Phase Error Between Channels
I
DIF0
15
DIF1
11
DEM0 DEM1
1
2
VA+
3
VD+
6
16
CMFILT
LRCK 7
SCLK 9
10
SDATA
Serial Input
Interface
De-emphasis
Voltage Reference
Interpolator
Delta-Sigma
Modulator
DAC
Analog
Low-Pass
Filter
14
AOUTL
AUTO_MUTE
12
Interpolator
Delta-Sigma
Modulator
8
MCLK
DAC
4
Analog
Low-Pass
Filter
13
AOUTR
5
DGND
AGND
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright
©
Cirrus Logic, Inc. 1997
(All Rights Reserved)
DEC ‘97
DS190F1
1
CS4327
ANALOG CHARACTERISTICS
(T
A
= 25 °C; Internal SCLK; Full-Scale Output Sine wave, 997 Hz;
12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; R
L
= 10 kΩ; VD+ = VA+ = 5 V;
Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted, unless otherwise spec-
ified.)
Parameter
Specified Temperature Operating Range
Symbol
T
A
(Note 1)
20-Bit
(A-Weighted)
18-Bit
(A-Weighted)
16-Bit
(A-Weighted)
Total Harmonic Distortion + Noise
20-Bit
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
(Note 2)
THD+N
-87
-
-33
-
-
-
-
-
-
-
-
-
-
0
-
0.5465
72
-
-
-93
-77
-37
-93
-77
-37
-93
-77
-37
108
-105
±0.1
±0.5
-
-
-
-
25/Fs
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.4535
±0.002
-
-
-
±0.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBFS
dB
dB
deg
Fs
dB
Fs
dB
s
dB
93
96
-
-
-
-
97
100
97
100
93
95
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Min
-10
Typ
-
Max
70
Unit
°C
Dynamic Performance
Dynamic Range
18-Bit
16-Bit
Idle Channel Noise / Signal-to-Noise-Ratio
Interchannel Isolation
(1 kHz)
Combined Digital and Analog Filter Characteristics
Frequency Response 10 Hz to 20 kHz
Fs = 48 kHz
Deviation from linear phase
Passband: to -0.1 dB corner
Passband Ripple
StopBand
StopBand Attenuation
Group Delay
(Note 3)
De-emphasis Error
Notes: 1. Triangular PDF Dithered Data
2. Auto-mute enabled. See parameter definitions.
3. Group Delay for Fs = 48 kHz
25/48 kHz = 520 µs
2
DS190F1
CS4327
ANALOG CHARACTERISTICS
Parameter
(Continued)
Symbol
Min
-
-
-
0.95
6
-
-
Typ
0.1
±2
200
1.0
-
-
2.3
Max
-
±5
-
1.05
-
100
-
Unit
dB
%
ppm/°C
Vrms
kΩ
pF
V
dc Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Output
Full Scale Output Voltage
Load Resistance
Load Capacitance
Output Common Mode Voltage
POWER AND THERMAL CHARACTERISTICS
(T
A
= 25 °C; Internal SCLK; Full-Scale Output
Sine wave, 997 Hz; 12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; R
L
= 10 kΩ;
VD+ = VD+ = 5 V; Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted,
unless otherwise specified.)
Parameter
Power Supply Current
Normal Operation
Symbol
IA+
ID+
(IA+) + (ID+)
Power Down (IA+) + (ID+)
Min
-
-
-
-
-
-
PSRR
Θ
JA
-
-
-
Typ
25
12
37
300
185
1.5
60
-
120
Max
-
-
43
-
215
-
-
135
-
Unit
mA
mA
mA
µA
mW
mW
dB
°C
°C/W
Power Dissipation
Power Supply Rejection Ratio (1 kHz)
Allowable Junction Temperature
Junction to Ambient Thermal Impedance
Normal Operation
Power-down
DS190F1
3
CS4327
SWITCHING CHARACTERISTICS
C
L
= 20 pF)
Parameter
Input Sample Rate
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK/LRCK = 512
MCLK/LRCK = 512
MCLK/LRCK = 384
MCLK/LRCK = 384
MCLK/LRCK = 256
MCLK/LRCK = 256
t
sclkl
t
sclkh
t
sclkw
t
slrd
t
slrs
t
sdlrs
t
sdh
SCLK/LRCK = 64
t
sclkw
t
sclkr
t
sdlrs
t
sdh
t
sdh
Symbol
Fs
Min
1
10
10
21
21
31
31
20
20
1
-------------------
-
128(Fs)
(T
A
= 25 °C; VA+ = 5.0 V; Inputs: Logic 0 = 0 V, Logic 1 = VD+,
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t sc lk w
-----------------
-
2
Max
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
20
20
20
20
1
----------------
-
64(Fs)
Internal SCLK Mode
SCLK Period
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
-
1
------------------- + 10
-
512(Fs)
1
------------------- + 15
-
512(Fs)
1
------------------- + 15
-
384(Fs)
-
-
-
SCLK rising to SDATA hold time MCLK/LRCK = 256 or 512
SCLK rising to SDATA hold time
MCLK/LRCK = 384
4
DS190F1
CS4327
LRCK
t
slrs
t
sclkl
t
sclkh
t
slrd
SCLK
t
t
sdlrs
sdh
SDATA
External Serial Mode Input Timing
LRCK
t
sclkr
SDATA
t
t
sclkw
sdlrs
t
sdh
*INTERNAL SCLK
Internal Serial Mode Input Timing.
*
The SCLK pin must be terminated to ground.
The SCLK pulses shown are internal to the CS4327
DS190F1
5
