CS4362A
114 dB, 192 kHz
6
-channel D/A Converter
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
– On-chip 50 kHz filter
– Matched PCM and DSD analog output
levels
Selectable Digital Filters
Volume Control with 1-dB Step Size and Soft
Ramp
Low Clock Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Description
The CS4362A is a complete 6-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow-
ing this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
The CS4362A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage.
The CS4362A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
ORDERING INFORMATION
See page 41.
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Level Translator
Hardware Mode or
I
2
C/SPI Software Mode
Control Data
Register/Hardware
Configuration
Internal Voltage
Reference
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
PCM Serial
Audio Input
6
Volume
Controls
Digital
Filters
Multi-bit
∆Σ
Modulators
Serial Interface
Level Translator
Switch-Cap
DAC and
Analog Filters
6
6
Six Channels of
Differential
Outputs
DSD Audio
Input
DSD Processor
-50 kHz filter
External Mute
Control
6
Mute Signals
http://www.cirrus.com
Copyright
©
Cirrus Logic, Inc. 2005
(All Rights Reserved)
APR '05
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CS4362A
TABLE OF CONTENTS
1. PIN DESCRIPTION..................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8
3. APPLICATIONS ....................................................................................................................... 20
3.1 Master Clock..................................................................................................................... 20
3.2 Mode Select...................................................................................................................... 20
3.3 Digital Interface Formats .................................................................................................. 22
3.4 Oversampling Modes........................................................................................................ 23
3.5 Interpolation Filter ............................................................................................................. 23
3.6 De-Emphasis .................................................................................................................... 23
3.7 ATAPI Specification .......................................................................................................... 24
3.8 Direct Stream Digital (DSD) Mode.................................................................................... 25
3.9 Grounding and Power Supply Arrangements ................................................................... 25
3.9.1 Capacitor Placement............................................................................................ 25
3.10 Analog Output and Filtering ............................................................................................ 25
3.11 Mute Control ................................................................................................................... 26
3.12 Recommended Power-Up Sequence ............................................................................. 27
3.12.1 Hardware Mode ................................................................................................. 27
3.12.2 Software Mode................................................................................................... 27
3.13 Recommended Procedure for Switching Operational Modes......................................... 27
3.14 Control Port Interface ..................................................................................................... 28
3.14.1 MAP Auto Increment.......................................................................................... 28
3.14.2 I
2
C Mode............................................................................................................ 28
3.14.2.1 I
2
C Write ............................................................................................ 28
3.14.2.2 I
2
C Read ............................................................................................ 29
3.14.3 SPI™ Mode........................................................................................................ 30
3.14.3.1 SPI Write............................................................................................ 30
3.15 Memory Address Pointer (MAP)
............................................................................... 30
4. REGISTER QUICK REFERENCE ............................................................................................ 31
5. REGISTER DESCRIPTION ...................................................................................................... 32
5.1 Mode Control 1 (address 01h) .......................................................................................... 32
5.1.1 Control Port Enable (CPEN) ................................................................................ 32
5.1.2 Freeze Controls (Freeze)..................................................................................... 32
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv) ............................................................ 32
5.1.4 DAC Pair Disable (DACx_DIS) ............................................................................ 32
5.1.5 Power Down (PDN).............................................................................................. 33
5.2 Mode Control 2 (address 02h) ......................................................................................... 33
5.2.1 Digital Interface Format (dif) ................................................................................ 33
5.2.2 Mode Control 3 (address 03h) ............................................................................ 34
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 34
5.2.4 Single Volume Control (Snglvol) .......................................................................... 34
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 35
5.2.6 MUTEC Polarity (MUTEC+/-)............................................................................... 35
5.2.7 Auto-Mute (AMUTE) ........................................................................................... 35
5.2.8 Mute Pin Control (MUTEC1, MUTEC0) ............................................................... 35
5.3 Filter Control (address 04h) ............................................................................................. 36
5.3.1 Interpolation Filter Select (FILT_SEL).................................................................. 36
5.3.2 De-Emphasis Control (DEM) ............................................................................... 36
5.3.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 36
5.4 Invert Control (address 05h) ............................................................................................ 37
5.4.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37
5.5 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
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CS4362A
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch) ............................................. 37
5.5.1 Channel A Volume = Channel B Volume (A=B)................................................... 37
5.5.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................ 37
5.5.3 Functional Mode (FM).......................................................................................... 38
5.6 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) .......................................... 39
5.6.1 Mute (MUTE) ....................................................................................................... 39
5.6.2 Volume Control (xx_VOL) .................................................................................... 39
5.7 Chip Revision (address 12h) ........................................................................................... 40
5.7.1 Part Number ID (part) [Read Only] ...................................................................... 40
6. PARAMETER DEFINITIONS.................................................................................................... 41
7. REFERENCES.......................................................................................................................... 41
8. ORDERING INFORMATION .................................................................................................... 41
9. PACKAGE DIMENSIONS ........................................................................................................ 42
10. APPENDIX ............................................................................................................................. 43
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CS4362A
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing.....................................................................................................
Figure 2. Direct Stream Digital - Serial Audio Input Timing.......................................................................
Figure 3. Control Port Timing - I
2
C Format ...............................................................................................
Figure 4. Control Port Timing - SPI Format...............................................................................................
Figure 5. Typical Connection Diagram, Software Mode............................................................................
Figure 6. Typical Connection Diagram, Hardware Mode ..........................................................................
Figure 7. Format 0 - Left-Justified up to 24-bit Data .................................................................................
Figure 8. Format 1 - I
2
S up to 24-bit Data.................................................................................................
Figure 9. Format 2 - Right-Justified 16-bit Data ........................................................................................
Figure 10. Format 3 - Right-Justified 24-bit Data ......................................................................................
Figure 11. Format 4 - Right-Justified 20-bit Data ......................................................................................
Figure 12. Format 5 - Right-Justified 18-bit Data ......................................................................................
Figure 13. De-Emphasis Curve.................................................................................................................
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ..................................................................
Figure 15. Full-Scale Output .....................................................................................................................
Figure 16. Recommended Output Filter....................................................................................................
Figure 17. Control Port Timing, I
2
C Mode.................................................................................................
Figure 18. Control Port Timing, SPI mode ................................................................................................
Figure 19. Single-Speed (fast) Stopband Rejection..................................................................................
Figure 20. Single-Speed (fast) Transition Band ........................................................................................
Figure 21. Single-Speed (fast) Transition Band (detail) ............................................................................
Figure 22. Single-Speed (fast) Passband Ripple ......................................................................................
Figure 23. Single-Speed (slow) Stopband Rejection ................................................................................
Figure 24. Single-Speed (slow) Transition Band.......................................................................................
Figure 25. Single-Speed (slow) Transition Band (detail)...........................................................................
Figure 26. Single-Speed (slow) Passband Ripple.....................................................................................
Figure 27. Double-Speed (fast) Stopband Rejection ................................................................................
Figure 28. Double-Speed (fast) Transition Band.......................................................................................
Figure 29. Double-Speed (fast) Transition Band (detail)...........................................................................
Figure 30. Double-Speed (fast) Passband Ripple.....................................................................................
Figure 31. Double-Speed (slow) Stopband Rejection ...............................................................................
Figure 32. Double-Speed (slow) Transition Band .....................................................................................
Figure 33. Double-Speed (slow) Transition Band (detail) .........................................................................
Figure 34. Double-Speed (slow) Passband Ripple ...................................................................................
Figure 35. Quad-Speed (fast) Stopband Rejection ...................................................................................
Figure 36. Quad-Speed (fast) Transition Band .........................................................................................
Figure 37. Quad-Speed (fast) Transition Band (detail) .............................................................................
Figure 38. Quad-Speed (fast) Passband Ripple .......................................................................................
Figure 39. Quad-Speed (slow) Stopband Rejection..................................................................................
Figure 40. Quad-Speed (slow) Transition Band........................................................................................
Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................
Figure 42. Quad-Speed (slow) Passband Ripple......................................................................................
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LIST OF TABLES
Table 1. Common Clock Frequencies........................................................................................... 20
Table 2. Digital Interface Format, Stand-Alone Mode Options...................................................... 21
Table 3. Mode Selection, Stand-Alone Mode Options .................................................................. 21
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 21
Table 5. Digital Interface Formats - PCM Mode............................................................................ 33
Table 6. Digital Interface Formats - DSD Mode ............................................................................ 33
Table 7. ATAPI Decode ................................................................................................................ 38
Table 8. Example Digital Volume Settings .................................................................................... 39
Table 9. Revision History ............................................................................................................. 47
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