CS8405A
96 kHz Digital Audio Interface Transmitter
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Transmitter
+5.0 V Digital Supply (VD+)
+3.3 V or 5.0 V Digital Interface (VL+)
On-chip channel status and user bit buffer
memories allow block-sized updates.
Flexible 3-wire Serial Digital Audio Input
Port
Up to 96 kHz Frame Rate
Microcontroller Write Access to Channel
Status and User Bit Data
On-chip Differential Line Driver
Generates CRC Codes and Parity Bits
Standalone Mode Allows use Without a
Microcontroller
General Description
The CS8405A is a monolithic CMOS device which en-
codes and transmits audio data according to the AES3,
IEC60958, S/PDIF, or EIAJ CP1201. The CS8405A ac-
cepts audio and digital data, which is then multiplexed,
encoded, and driven onto a cable.
The audio data is input through a configurable, 3-wire in-
put port. The channel status and user bit data are input
through an SPI or
I²C
microcontroller port, and may be
assembled in block-sized buffers. For systems with no
microcontroller, a standalone mode allows direct access
to channel status and user bit data pins.
Target applications include A/V Receivers, CD-R, DVD
receivers, digital mixing consoles, effects processors,
set-top boxes, and computer or automotive audio
systems.
ORDERING INFORMATION
CS8405A-CS
CS8405A-CZ
CS8405A-CZZ, Lead Free
CS8405A-IS
CS8405A-IZ
CDB8415A
28-pin SOIC
-10 to
28-pin TSSOP -10 to
28-pin TSSOP -10 to
28-pin SOIC
-40 to
28-pin TSSOP -40 to
Evaluation Board
+70°C
+70°C
+70°C
+85°C
+85°C
I
VD+
VL+ DGND
RXP
C & U bit
Data
Buffer
AES3
S/PDIF
Encoder
TXP
Driver
TXN
ILRCK
ISCLK
SDIN
Serial
Audio
Input
Misc.
Control
RST
Control
Port &
Registers
Output
Clock
Generator
H/S
U TCBL SDA/
SCL/ AD1/ AD0/ AD2 INT
CDOUT CCLK CDIN CS
OMCK
©
Cirrus Logic, Inc.
www.cirrus.com
Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
Aug ‘04
DS469F2
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CS8405A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
DC ELECTRICAL CHARACTERISTICS................................................................................... 5
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 5
DIGITAL INTERFACE SPECIFICATIONS................................................................................ 5
TRANSMITTER CHARACTERISTICS ..................................................................................... 5
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE....................................... 9
2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 10
3. GENERAL DESCRIPTION ..................................................................................................... 11
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 11
4. THREE-WIRE SERIAL INPUT AUDIO PORT ........................................................................ 11
5. AES3 TRANSMITTER ............................................................................................................ 13
5.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 13
5.2 TXN and TXP Drivers ...................................................................................................... 13
5.3 Mono Mode Operation ..................................................................................................... 13
6. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 15
6.1 SPI Mode ......................................................................................................................... 15
6.2 I²C Mode .......................................................................................................................... 15
6.3 Interrupts .......................................................................................................................... 16
7. CONTROL PORT REGISTER SUMMARY ........................................................................... 17
7.1 Memory Address Pointer (MAP) ....................................................................................... 17
8. CONTROL PORT REGISTER BIT DEFINITIONS .................................................................. 18
8.1 Control 1 (01h) .................................................................................................................. 18
8.2 Control 2 (02h) .................................................................................................................. 18
8.3 Data Flow Control (03h).................................................................................................... 19
8.4 Clock Source Control (04h)............................................................................................... 19
8.5 Serial Audio Input Port Data Format (05h)........................................................................ 20
8.6 Interrupt 1 Status (07h) (Read Only)................................................................................. 21
8.7 Interrupt 2 Status (08h) (Read Only)................................................................................. 21
8.8 Interrupt 1 Mask (09h)....................................................................................................... 21
8.9 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ......................................... 22
8.10 Interrupt 2 Mask (0Ch) .................................................................................................... 22
8.11 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)....................................... 22
8.12 Channel Status Data Buffer Control (12h) ...................................................................... 23
8.13 User Data Buffer Control (13h) ....................................................................................... 23
8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 24
8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ................................................. 24
9. PIN DESCRIPTION - SOFTWARE MODE .......................................................................... 25
10. HARDWARE MODE ............................................................................................................. 27
10.1 Channel Status, User and Validity Data ......................................................................... 27
10.2 Serial Audio Port Formats .............................................................................................. 27
11. PIN DESCRIPTION - HARDWARE MODE ....................................................................... 29
12. APPLICATIONS .................................................................................................................... 31
12.1 Reset, Power Down and Start-up .................................................................................. 31
12.2 ID Code and Revision Code .......................................................................................... 31
12.3 Power Supply, Grounding, and PCB layout ................................................................... 31
12.4 Synchronization of Multiple CS8405As .......................................................................... 31
13. PACKAGE DIMENSIONS ................................................................................................... 32
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CS8405A
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPO-
NENTS .................................................................................................................................. 34
14.1 AES3 Transmitter External Components ....................................................................... 34
14.2 Isolating Transformer Requirements ............................................................................. 34
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 35
15.1 AES3 Channel Status(C) Bit Management .................................................................... 35
15.1.1 Accessing the E buffer ...................................................................................... 35
15.1.2 Serial Copy Management System (SCMS) ....................................................... 36
15.1.3 Channel Status Data E Buffer Access .............................................................. 36
15.2 AES3 User (U) Bit Management .................................................................................... 36
15.2.1 Mode 1: Transmit All Zeros ............................................................................... 36
15.2.2 Mode 2: Block Mode ......................................................................................... 36
16. REVISION HISTORY ............................................................................................................ 37
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ...................................................................................... 7
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 7
Figure 3. SPI Mode timing............................................................................................................... 8
Figure 4. I²C Mode timing................................................................................................................ 9
Figure 5. Recommended Connection Diagram for Software Mode .............................................. 10
Figure 6. Serial Audio Input Example Formats ............................................................................. 12
Figure 7. AES3 Transmitter Timing for C, U, and V Pin Input Data .............................................. 14
Figure 8. Control Port Timing in SPI Mode ................................................................................... 15
Figure 9. Control Port Timing in I²C Mode .................................................................................... 16
Figure 10. Hardware Mode ........................................................................................................... 27
Figure 11. Professional Output Circuit .......................................................................................... 34
Figure 12. Consumer Output Circuit ............................................................................................. 34
Figure 13. TTL/CMOS Output Circuit............................................................................................ 34
Figure 14. Channel Status Data Buffer Structure.......................................................................... 35
Figure 15. Flowchart for Writing the E Buffer ................................................................................ 35
LIST OF TABLES
Table 1. Control Register Map Summary...................................................................................... 17
Table 2. Hardware Mode COPY/C and ORIG pin functions ......................................................... 27
Table 3. Hardware Mode Serial Audio Port Format Selection ...................................................... 28
Table 4. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode28
Table 5. Revision History .............................................................................................................. 37
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CS8405A
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
A
= 25°C.)
SPECIFIED OPERATING CONDITIONS
(DGND = 0 V, all voltages with respect to 0 V)
Parameter
Power Supply Voltage
(Note 1)
Ambient Operating Temperature:
‘-CS’ & ‘-CZ’
‘-IS’ & ‘-IZ’
Symbol
VD+
VL+
T
A
Min
4.5
2.85
-10
-40
Typ
5.0
3.3 or 5.0
-
-
Max
5.5
5.5
+70
+85
Units
V
V
°C
Notes: 1. I²C protocol is supported only in VL+ = 5.0 V mode.
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V; all voltages with respect to 0 V. Operation beyond these
limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Parameter
Power Supply Voltage
Input Current, Any Pin Except Supplies
Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
(Note 2)
Symbol
VD+,VL+
I
in
V
in
T
A
T
stg
Min
-
-
-0.3
-55
-65
Max
6.0
±10
(VL+) + 0.3
125
150
Units
V
mA
V
°C
°C
Notes: 2. Transient currents of up to 100 mA will not cause SCR latch-up.
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CS8405A
DC ELECTRICAL CHARACTERISTICS
(DGND = 0 V; all voltages with respect to 0 V.)
Parameters
Power-down Mode
(Note 3)
Supply Current in power down
VD+
VL+ = 3.3 V
VL+ = 5.0 V
VD+
VL+ = 3.3 V
VL+ = 5.0 V
VD+
VL+ = 3.3 V
VL+ = 5.0 V
-
-
-
-
-
-
-
-
-
20
60
60
6.3
30.1
46.5
6.6
44.8
76.6
-
-
-
-
-
-
-
-
-
µA
µA
µA
mA
mA
mA
mA
mA
mA
Symbol
Min
Typ
Max
Units
Normal Operation
(Note 4)
Supply Current at 48 kHz frame rate
Supply Current at 96 kHz frame rate
Notes: 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
4. Normal operation is defined as RST = HI.
DIGITAL INPUT CHARACTERISTICS
Parameters
Input Leakage Current
Symbol
I
in
Min
-
Typ
±1
Max
±10
Units
µA
DIGITAL INTERFACE SPECIFICATIONS
(DGND = 0 V; all voltages with respect to 0 V.)
Parameters
High-Level Output Voltage (I
OH
= -3.2 mA), except TXP/TXN
Low-Level Output Voltage (I
OL
= 3.2 mA), except TXP/TXN
High-Level Output Voltage, TXP, TXN
Low-Level Output Voltage, TXP, TXN
High-Level Input Voltage
Low-Level Input Voltage
Notes: 5.
(Note 5)
(23 mA at VL+ = 5.0 V)
(15.2 mA at VL+ = 3.3 V)
(23 mA at VL+ = 5.0 V)
(15.2 mA at VL+ = 3.3 V)
V
IH
V
IL
Symbol
V
OH
V
OL
Min
(VL+) - 1.0
-
(VL+) - 0.7
(VL+) - 0.7
-
-
2.0
-0.3
Max
-
0.4
-
-
0.7
0.7
(VL+) + 0.3
0.4/0.8
Units
V
V
V
V
V
V
V
V
At 5.0 V mode, V
IL
= 0.8 V (Max), at 3.3 V mode, V
IL
=0.4 V (Max).
TRANSMITTER CHARACTERISTICS
Parameters
TXP Output Resistance
TXN Output Resistance
VL+ = 5.0 V
VL+ = 3.3 V
VL+ = 5.0 V
VL+ = 3.3 V
Symbol
R
TXP
R
TXN
Min
-
-
-
-
Typ
26
40
26
40
Max
-
-
-
-
Units
Ω
Ω
Ω
Ω
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