®
®
CDS-1401
14-Bit, Fast-Settling
Correlated Double Sampling Circuit
INNOVATION and EXCELLENCE
FEATURES
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•
•
•
•
•
•
•
•
•
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Use with 10 to 14-bit A/D converters
1.25 Megapixels/second minimum throughput (14 bits)
±10V input/output ranges, Gain = –1
Low noise, 200µVrms
Two independent S/H amplifiers
Gain matching between S/H's
Offset adjustments for each S/H
Four external A/D control lines
Small package, 24-pin ceramic DDIP
Low power, 700mW
Low cost
INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
FUNCTION
OFFSET ADJUST V1
OFFSET ADJUST I1
ANALOG INPUT 1
ANALOG INPUT 2
ANALOG GROUND
S/H1 OUT
S/H1 ROUT
S/H2 SUMMING NODE
OFFSET ADJUST V2
OFFSET ADJUST I2
S/H1 COMMAND
S/H2 COMMAND
PIN
24
23
22
21
20
19
18
17
16
15
14
13
FUNCTION
+15V ANALOG SUPPLY
ANALOG GROUND
V OUT
ANALOG GROUND
A/D CLOCK2
A/D CLOCK2
A/D CLOCK1
A/D CLOCK1
+5V DIGITAL SUPPLY
DIGITAL GROUND
ANALOG GROUND
–15V ANALOG SUPPLY
GENERAL DESCRIPTION
The CDS-1401 is an application-specific, correlated double
sampling (CDS) circuit designed for electronic-imaging
applications that employ CCD’s (charge coupled devices) as
their photodetector. The CDS-1401 has been optimized for
use in digital video applications that employ 10 to 14-bit A/D
converters. The low-noise CDS-1401 can accurately
determine each pixel’s true video signal level by sequentially
sampling the pixel’s offset signal and its video signal and
subtracting the two. The result is that the consequences of
residual charge, charge injection and low-frequency “kTC”
noise on the CCD’s output floating capacitor are effectively
eliminated. The CDS-1401 can also be used as a dual
sample-hold amplifier in a data acquisition system.
The CDS-1401 contains two sample-hold amplifiers and
appropriate support/control circuitry. Features include
independent offset-adjust capability for each S/H, adjustment
for matching gain between the two S/H’s, and four control
lines for triggering the A/D converter used in conjunction with
the CDS-1401. The CDS circuit’s “ping-pong” timing
approach (the offset signal of the “n+1” pixel can be acquired
while the video output of the “nth” pixel is being converted)
guarantees a minimum throughput, in a 14-bit application, of
1.25MHz. In other words, the true video signal (minus offset)
will be available
(continued on page 4-5)
100k
Ω
OFFSET ADJUST V1 1
1k
Ω
100Ω
OFFSET ADJUST I1 2
1k
Ω
ANALOG INPUT 1
3
C
H
= 100pF
–
S/H 1
+
6
S/H1 OUT
7
S/H1 ROUT
OPTIONAL
100kΩ
OFFSET ADJUST V2 9
1k
Ω
OFFSET ADJUST I2 10
1k
Ω
ANALOG INPUT 2
4
C
H
= 100pF
–
S/H 2
+
8
S/H2
SUMMING NODE
900Ω
22 V OUT
S/H1 COMMAND 11
18 A/D CLOCK 1
17 A/D CLOCK 1
S/H2 COMMAND 12
19 A/D CLOCK 2
20 A/D CLOCK 2
5, 14, 21, 23
ANALOG GROUND
24
+15V SUPPLY
13
–15V SUPPLY
16
+5V DIGITAL
SUPPLY
15
DIGITAL
GROUND
Figure 1. CDS-1401 Functional Block Diagram
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.)
•
Tel: (508) 339-3000 Fax: (508) 339-6356
•
For immediate assistance (800) 233-2765
®
®
CDS-1401
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+15V Supply
(Pin 24)
–15V Supply
(Pin 13)
+5V Supply
(Pin 16)
Digital Inputs
(Pins 11, 12)
Analog Inputs
(Pins 3, 4)
Lead Temp.
(10 seconds)
LIMITS
0 to +16
0 to –16
0 to +6
–0.3 to +V
DD
+0.3
±12
300
UNITS
Volts
Volts
Volts
Volts
Volts
°C
PHYSICAL/ENVIRONMENTAL
PARAMETERS
Operating Temp. Range, Case
CDS-1401MC
CDS-1401MM
Thermal Impedance
θjc
θca
Storage Temperature Range
Package Type
Weight
MIN.
0
–55
—
—
–65
TYP.
—
—
5
22
—
MAX.
+70
+125
—
—
+150
UNITS
°C
°C
°C/W
°C/W
°C
24-pin, metal-sealed, ceramic DDIP
0.42 ounces(12 grams)
FUNCTIONAL SPECIFICATIONS
(T
A
= +25°C, ±Vcc = ±15V, +V
DD
= +5V, pixel rate = 1.25MHz, and a minimum warmup time of two minutes unless otherwise noted.)
+25°C
ANALOG INPUTS
Input Voltage Range
Input Resistance
Input Capacitance
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
PERFORMANCE
Sample Mode Offset Error
- S/H1
Gain Error
- S/H1
Pedestal
- S/H1
Sample Mode Offset Error
- S/H2
Gain Error
- S/H2
Pedestal
- S/H2
Sample Mode Offset Error
- CDS
Differential Gain Error
- CDS
Pedestal
- CDS
Pixel Rate
(14-bit settling)
Input Bandwidth, ±5V
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
(to ±0.003%, 10V step)
Hold Mode Settling Time
(to ±0.15mV)
Noise
Feedthrough Rejection
Overvoltage Recovery Time
S/H Saturation Voltage
Droop Rate
ANALOG OUTPUTS
Output Voltage Range
Output Impedance
Output Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Pins 3 and 4.
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
+3.9
—
—
—
—
—
—
—
—
+0.4
–4
+4
Volts
Volts
mA
mA
±10
—
—
—
0.5
—
—
—
±20
±10
—
—
—
0.5
—
—
—
±20
±10
—
—
—
0.5
—
—
—
±20
Volts
Ohms
mA
—
—
—
—
—
—
—
—
—
1.25
—
—
—
—
—
—
—
—
—
—
—
—
±1
±0.2
±15
±1
±0.2
±15
±1
±0.25
±15
—
7
5
±80
10
5
340
TBD
200
72
400
±12.5
±0.004
±10
±1
±35
±10
±1
±35
±10
±1
±35
—
—
—
—
—
—
400
—
—
—
—
—
±0.02
—
—
—
—
—
—
—
—
—
1.25
—
—
—
—
—
—
—
—
—
—
—
—
±2
±0.25
±15
±2
±0.25
±15
±2
±0.3
±15
—
7
5
±80
10
5
350
TBD
200
72
400
±12.5
±0.4
±10
±1
±35
±10
±1
±35
±10
±1
±35
—
—
—
—
—
—
400
—
—
—
—
—
±2
—
—
—
—
—
—
—
—
—
1.25
—
—
—
—
—
—
—
—
—
—
—
—
±4
±0.3
±15
±4
±0.3
±15
±4
±0.35
±15
—
7
5
±80
10
5
350
TBD
200
72
400
±12.5
±0.8
±10
±1.5
±35
±10
±1.5
±35
±10
±1.5
±35
—
—
—
—
—
—
400
—
—
—
—
—
±4
mV
%
mV
mV
%
mV
mV
%
mV
MHz
MHz
MHz
V/µs
ns
ps rms
ns
ns
µVr ms
dB
ns
Volts
mV/µs
+2
—
—
—
—
—
—
—
—
+0.8
+10
–10
+2
—
—
—
—
—
—
—
—
+0.8
+10
–10
+2
—
—
—
—
—
—
—
—
+0.8
+10
–10
Volts
Volts
µA
µA
MIN.
±10
—
—
TYP.
—
1000
7
MAX.
—
—
15
MIN.
±10
—
—
0 to +70°C
TYP.
—
1000
7
MAX.
—
—
15
MIN.
±10
—
—
–55 to +125°C
TYP.
—
1000
7
MAX.
—
—
15
UNITS
Volts
Ohms
pF
See Figure 4 for relationship between input voltage, accuracy, and acquisition time.
Pins 6 and 22.
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®
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CDS-1401
+25°C
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
MIN.
+14.75
–14.75
+4.75
—
—
—
—
—
TYP.
+15.0
–15.0
+5.0
+23
–23
+1
700
100
MAX.
+15.25
–15.25
+5.25
+27
–27
+2
850
—
MIN.
+14.75
–14.75
+4.75
—
—
—
—
—
0 to +70°C
TYP.
+15.0
–15.0
+5.0
+23
–23
+1
700
100
MAX.
+15.25
–15.25
+5.25
+27
–27
+2
850
—
MIN.
+14.75
–14.75
+4.75
—
—
—
—
—
–55 to +125°C
TYP.
+15.0
–15.0
+5.0
+23
–23
+1
700
100
MAX.
+15.25
–15.25
+5.25
+27
–27
+2
850
—
UNITS
Volts
Volts
Volts
mA
mA
mA
mW
dB
GENERAL DESCRIPTION
(continued)
at the output of the CDS-1401 every 800ns. This correlates
with the fact that an acquisition time of 400ns is required for
each internal S/H amplifier (10V step setting to ±0.003%). The
input and output of the CDS-1401 can swing up to ±10 Volts.
The functionally complete CDS-1401 is packaged in a single,
24-pin, ceramic DDIP. It operates from ±15V and +5V supplies
and consumes 700mW. Though the CDS-1401’s approach to
CDS appears straightforward (see Description of Operation),
the circuit actually exploits an elegant architecture whose
tradeoffs enable it to offer wide-bandwidth, low-noise and high-
throughput combinations unachievable until now. The CDS-
1401 is a generic type of circuit that can be used with almost
any 10 to 14-bit A/D converter. However, DATEL does offer
A/D converters that are optimized for use with the CDS-1401.
FUNCTIONAL DESCRIPTION
Correlated Double Sampling
All photodetector elements (photodiodes, photomultiplier tubes,
focal plane arrays, charge coupled devices, etc.) have unique
output characteristics that call for specific analog-signal-
processing (ASP) functions at their outputs. Charge coupled
devices (CCD’s), in particular, display a number of unique
characteristics. Among them is the fact that the “offset error”
associated with each individual pixel (i.e., the apparent
photonic content of that pixel after having had no light incident
upon it) changes each and every time that particular pixel is
accessed.
Most of us think of an offset as a constant parameter that
either can be compensated for (by performing an offset
adjustment) or can be measured, recorded, and subtracted
from subsequent readings to yield more accurate data.
Contending with an offset that varies from reading to reading
requires measuring and recording (or capturing and storing)
the offset each and every time, so it can be subtracted from
each subsequent data reading.
The “double sampling” aspect of CDS refers to the operation of
sampling and storing/recording a given pixel’s offset and then
sampling the same pixel’s output an instant later (with both the
offset and the video signal present) and subsequently
subtracting the two values to yield what is referred to as the
“valid video” output for that pixel.
The “correlated” in CDS refers to the fact that the two samples
must be taken close together in time because the offset is
constantly varying. Reasons for this phenomena are
discussed below.
At the output of all CCD’s, transported pixel charge (electrons)
is converted to a voltage by depositing the charge onto a
capacitor (usually called the output or “floating” capacitor).
The voltage that develops across this capacitor is obviously
proportional to the amount of deposited charge (i.e., the
number of electrons) according to
∆V
=
∆Q/C.
Once settled,
the resulting capacitor voltage is buffered and brought to the
CCD’s output pin as a signal whose amplitude is proportional
to the total number of photons incident upon the relevant pixel.
After the output signal has been recorded, the floating
capacitor is discharged (“reset”, “clamped”, “dumped”) and
made ready to accept charge from the next pixel. This is
when the problems begin. (This is a somewhat oversimplified
TECHNICAL NOTES
1. To achieve specified performance, all power supply pins
should be bypassed with 2.2µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. All ANALOG
GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND
(pin 15) pins should be tied to a large analog ground plane
beneath the package.
2. In the CDS configuration, to avoid saturation of the S/H
amplifiers, the maximum analog inputs and conditions are
as follows:
ANALOG INPUT 1 < ±12V
(ANALOG INPUT 1 – ANALOG INPUT 2) < ±12V
3. The combined video and reference/offset signal from the
CCD array must be applied to S/H2, while the reference/
offset signal is applied to S/H1.
4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE)
to either pin 6 (S/H1 OUT), through a 200 Ohm
potentiometer, or directly to pin 7 (S/H1 ROUT). In both
cases, the CCD's output is tied to pins 3 (ANALOG INPUT
1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the
200Ω potentiometer is for gain matching.
5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8
(S/H2 SUMMING NODE) floating. Pin 6 (S/H1 OUT) will be
the output of S/H1 and pin 22 (V OUT) will be the output
of S/H2.
6. See Figure 4 for acquisition time versus accuracy and input
voltage step amplitude.
3
®
®
CDS-1401
explanation in that the floating capacitor is not usually
“discharged” but, in fact, “recharged” to some predetermined
dc voltage, usually called the “reference level”. The pixel offset
appears as an output deviation from that reference level.)
The floating capacitor is normally discharged (charged) via a
shunt switch (typically a FET structure) that has a non-zero
“on” resistance. When the switch is on, its effective series
resistance exhibits thermal noise (Johnson noise) due to the
random motion of thermally energized charge. Because the
shunt switch is in parallel with the floating capacitor, the
instantaneous value of the thermal noise (expressed in either
Volts or electrons) appears across the cap. When the shunt
switch is opened, charge/voltage is left on the floating cap.
The magnitude of this “captured noise voltage” is a function of
absolute temperature (T), the value of the floating capacitor (C)
and Boltzman’s constant (k). It is commonly referred to as
“kTC” noise.
The second contributor to the constantly varying pixel offsets
is the fact that, at high pixel rates, the floating capacitor never
has time to fully discharge (charge) during the period in which
its shunt switch is closed. There is always some “residual”
charge left on the cap, and the amount of this charge varies
as a function of what was the total charge held during the
previous pixel. This amount of residual charge is, in fact,
deterministic (if you know the previous charge and the number
of time constants in the discharge period), however, it is less
of a contributor than kTC noise.
The third major contributor to pixel offset is the fact that as the
shunt FET is turned off, the voltage across (and the charge
stored on) its parasitic junction capacitances changes. The
result is an “injection” of excess charge onto the floating cap
causing a voltage step normally called a “pedestal”.
The fourth major contributor to pixel offset is a low-frequency
noise component (usually called 1/f noise or pink noise)
associated with the CCD’s output buffer amplifier.
Due to all of these contributing factors, "pixel offsets" vary from
sample to sample in an inconsistent, unpredictable manner.
Traditional Approach to CDS
There are a number of techniques for dealing with the varying-
offset idiosyncrasy of CCD’s. The most prevalent has been
what can be called the “sample-sample-subtract” technique.
This approach requires the use of two high-speed sample-hold
(S/H) amplifiers and a difference amplifier. The first S/H is
used to acquire and hold a given pixel’s offset. Immediately
after that, the second S/H acquires and holds the same pixel’s
offset+video signal. After both the S/H outputs have fully
settled, the difference amplifier subtracts the offset from the
offset+video yielding the valid video signal.
CDS-1401 Approach (See Figure 1)
The DATEL CDS-1401 takes a slightly different, though clearly
superior, approach to CDS. It can be called the “sample-
subtract-sample” approach.
Note that the CDS-1401 has been configured to offer the
greatest amount of user flexibility. Its two S/H circuits function
independently. They have separate input and output pins.
Each has its own independent control lines. The control-line
signals are delayed, buffered, and brought back out of the
RESET N
RESET N+1
(CCD OUTPUT)
ANALOG INPUT
FOR CDS (Pins 3 and
4 are tied)
S/H 1 (Pin 11)
S/H 2 (Pin 12)
OFFSET N
OFFSET +
VIDEO N
OFFSET N+1
OFFSET +
VIDEO N+1
100ns typ.
HOLD
100ns typ.
30ns typ.
A/D CLOCK 1 (Pin 17)
HOLD
A/D CLOCK 1 (Pin 18)
30ns typ.
A/D CLOCK 2 (Pin 19)
A/D CLOCK 2 (Pin 20)
VIDEO SIGNAL N-1
VOLTAGE OUTPUT
VIDEO SIGNAL N
NOTE: Not Drawn to Scale
Figure 2. CDS-1401 Typical Timing Diagram
4
®
®
CDS-1401
package so they can be used to control other circuit functions.
Each S/H has two pins for offset adjusting (if required), one for
current and one for voltage.
In normal operation, the output signal of the CCD is applied
simultaneously to the inputs (pins 3 and 4) of both S/H
amplifiers. S/H1 will normally be used to capture and hold
each pixel’s offset signal. Therefore, S/H1 is initially in its
signal-acquisition mode (logic “1” applied to pin 11, S/H1
COMMAND). This is also called the sample or track mode.
Following a brief interval during which the output of the CCD
and the output of S/H1 are allowed to settle, S/H1 is driven into
its hold mode by applying a logic “0” to pin 11. S/H1 is now
holding the pixel’s offset value.
In most straightforward configurations, the output of S/H1 is
connected to the summing node of S/H2 by connecting pin 7
(S/H1 ROUT) to pin 8 (S/H2 SUMMING NODE).
When the offset+video signal appears at the output of the
CCD, S/H2 is driven into its signal acquisition mode by
applying a logic “1” to pin 12 (S/H2 COMMAND).
S/H2 employs a current-summing architecture that subtracts
the output of S/H1 (the offset) from the output of the CCD
(offset+video) while acquiring only the difference signal (i.e.,
the valid video). A logic “0” subsequently applied to pin 12
drives S/H2 into its hold mode, and after a brief transient
settling time, the valid video signal appears at pin 22 (V OUT).
Timing Notes
See Figure 2, Typical Timing Diagram. It is advisable that
neither of the CDS-1401's S/H amplifiers be in their sample/
track mode when large, high-speed transients (normally
associated with clock edges) are occurring throughout the
system. This could result in the S/H amplifiers being driven
into saturation, and they may not recover in time to accurately
acquire their next signal.
For example, S/H1 should not be commanded into the sample
mode until all transients associated with the opening of the
shunt switch have begun to decay. Similarly, S/H2 should not
be driven into the sample mode until all transients associated
with the clocking of pixel charge onto the output capacitor have
begun to decay. Therefore, it is generally not a good practice
to use the same clock edge to drive S/H1 into hold (holding the
offset) and S/H2 into sample (to acquire the offset + video
signal).
S/H's that are in their signal-acquisition modes should be left
there as long as possible (so all signals can settle) and be
driven into their hold modes before any system transients
occur. In Figure 2, S/H1 is driven into the sample mode shortly
after the transient from the shunt switch has begun to decay.
S/H1 is then kept in the sample mode while the offset signal
and the S/H output settle. S/H1 is driven into hold just prior to
the system clock pulse(s) that transfers the next pixel charge
onto the output capacitor.
As soon as the transients/noise associated with the charge
transport begins to decay, S/H2 can be driven into the sample
mode. S/H2 can then be left in the sample mode until just
before the reset pulse for the output capacitor.
In Figure 2, S/H's 1 and 2 both have the same acquisition time.
If the pixel-to-pixel amplitude variation of offset signals is much
RESET
RESET
(CCD OUTPUT)
ANALOG INPUT
FOR CDS
(Pins 3 and 4 are tied)
OFFSET (N+1)
OFFSET +
VIDEO (N+1)
OFFSET (N+2)
OFFSET +
VIDEO (N+2)
S/H1
400ns
S/H2
400ns
30ns typ.
START CONVERT
90ns typ.
420ns
EOC
OUTPUT
DATA
DATA N-1 VALID
73ns max.
35ns max.
DATA N VALID
DATA N+1 VALID
Figure 3. CDS-1401 in Front of ADS-CCD1201 at f
CLK
= 1MHz
5
