Standard Products
CT2577 / CT2579
Remote Terminal & Bus Controller
for MIL-STD-1553 / 1760 & McAir
www.aeroflex.com/Avionics
May 31, 2005
FEATURES
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Complete RT & BC Protocol
Meets MIL-STD-1553 A/B & MIL-STD-1760 A/B
8 or 16 bit VME/MULTIBUS Interface
3K RAM
Dual Transceivers (1553 / 1760 or McAir)
+5V - Only Power Supply
Low Power (0.15 Watts per Channel)
Only Validated Messages Written to RAM
Self Test
Write / Readable Status & Bit Registers
Block Transfer Logic Guarantees Data Consistency
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Optional Data Wrap Around
Any Message may be Illegalized
Reduced Response Time Option (inh MC1F, RT & BC)
Optional 1760 checksum (RT & BC)
1760 Header word identification
Store Released Signal
Latched or Hard Wired RT Address
Comprehensive BC Error Checking
MIL-PRF-38534 Compliant Circuits Available
Designed for Commercial, Industrial and Aerospace Applications
Aeroflex is a Class H & K MIL-PRF-38534 Manufacturer
FUNCTIONAL BLOCK DIAGRAM
MANCHESTER DECODER
TRANSEIVER
16 BIT RECEIVE BUFFER
16 BIT TRANSMIT BUFFER
MANCHESTER DECODER
WATCHDOG TIMER
ENCODER / DECODER
REMOTE TERMINAL
STATE SEQUENCER
MANCHESTER DECODER
RT PROTOCOL
TRANSEIVER
16 BIT RECEIVE BUFFER
16 BIT TRANSMIT BUFFER
MANCHESTER DECODER
WATCHDOG TIMER
ENCODER / DECODER
COMMAND 1 REGISTER
WORD COUNTER
COMMAND 2 REGISTER
STATUS REGISTER
ERROR REGISTER
1K X 16 RAM
BROADCAST
RAM
1K X 16 RAM
TRANSMIT
1K X 16 RAM
RECEIVE
STATUS REGISTER
COMMAND REGISTER
WORD COUNTER
LAST COMMAND REG
BIT REGISTER
BLOCK TRANSFER LOGIC
ADDRESS GENERATOR
DMA CONTROLLER
DMA
STATE SEQUENCER
CMD / HDR
BUS 0
32 WORD
CMD / STATUS MEMORY
ADDRESS
BUS 1
STORE RELEASED
HEADER WORD IDENT
1760 CHECKSUM
GENERATION/VALIDATION
1760 OPTIONS
BUS CONTROL
STATE SEQUENCER
BC PROTOCOL
DATA BUS
TRANCEIVER
DATA BUS
TRANCEIVER
32 WORD
DATA MEMORY
SCDCT2577 Rev D
32 WORD
BLT MEMORY
8 / 16 BIT
SELECT
DATA
GENERAL DESCRIPTION
CT2577 provides the complete protocol for both Remote
Terminal and Bus Controller, supporting all types of message
transfers including all 15 mode codes, with comprehensive
error checking. Error handling of data is not required by the
subsystem.
The low power transceivers are capable of providing the output
voltage required by MIL-STD-1760 and are powered by a +5V
supply.
If sinusoidal (McAir) transceivers are required then the part
number becomes CT2579 This is the only difference between
CT2577 and CT2579
The user interface is pin selectable between 8 and 16 bit for
both VME and MULTIBUS. Addresses are referred to in
hexadecimal format and five bit address fields for simplicity in
correlating to the MIL-STD-1553 commands.
The device contains 3K words of main memory (1K receive,
1K transmit, and 1K broadcast receive).
A FIFO type memory is also provided for storing up to 32
command words (RT) or 32 status responses (BC). Access to
this memory is achieved by reading from location 0 00 00.
Discrete signals are provided to indicate the memory status (i.e.
full or empty). To reduce the processor intervention, the
command / status memory will only store commands that have
associated data.
A 32 word data buffer memory is used to store messages until
validation is complete. Only validated messages are written to
the main memory in a single burst. Data to be transmitted is
transferred from the main RAM to this buffer memory in a
single burst.
An optional 32 word BTL memory buffers the main memory to
the subsystem. This memory ensures data consistency by
“bursting” a message from the BTL memory to the main
memory (write) or from main memory to BTL memory (read)
uninterrupted after which the subsystem has access to this
memory at its leisure. This memory is not used for mode
commands as there is a maximum of only one associated data
word and data inconsistency cannot occur. The BTL memory
may be disabled by hardware or software.
Arbitration between the 1553 data bus and the processor bus is
fully automatic. When the main memory is required to be
accessed by the 1553 data bus, any current subsystem access to
the main RAM is completed first, thus ensuring no data is lost
or corrupted. The time the main memory is accessed by the
1553 data bus equates to 8.5 µS for command or status words,
plus 1 µS (transmit) or 500 nS (receive) for each data word.
The device has an optional RT wrap around capability. When
WRAPEN is active, data received at subaddress 1E (30)
remains stored in the data buffer memory (i.e. not transferred to
main memory). If followed by a transmit from subaddress 1E
the same data will be transmitted.
A self test feature can be enabled by the subsystem in software.
This function will initially set the device to be a Bus Controller
and transmit a message.
This message is received by the Remote Terminal via the
transceivers (online) or bypass the transceivers (offline). The
data and command transmitted by the Bus Controller can be
read back from the Remote Terminal by the subsystem.
There is an option within the device to reduce the response
time in order to conform to other standards such as 1553A and
McAir. In this mode subaddress 1F is allocated a normal
subaddress for both Remote Terminal and Bus Controller with
subaddress 00 being the only subaddress reserved for mode
commands.
Any message may be illegalised by applying an active low on
the NME discrete status input. The Remote Terminal will
respond with the Message Error bit set in the status and not use
the information received.
Configuration as a Remote Terminal and Bus Controller is
achieved by writing to address 1 00 00 and 1 00 01
respectively. The device defaults to Remote Terminal on power
up reset. A discrete signal BCNRT is provided to indicate the
device mode. The option is available for the Remote Terminal
to switch to Bus Control via the mode code Dynamic Bus
Control.
In the Bus Control mode all commands transferred to the
device are error checked and only valid legal commands are
allowed to be transmitted onto the 1553 data bus, any errors are
reported back to the host. Messages received on the 1553 data
bus destined for the host will only be stored in the main
memory once they have been completely validated.
A hardware implementation of the 1760 checksum algorithm
within the device may be enabled for both Remote Terminal
and Bus Controller via signal NENCHK. When transmitting,
the checksum word is inserted in the last word position, and
when receiving, a valid checksum word will generate the signal
NVALCHK as well as an open drain output (STATUS). The
STATUS output may be hard wired to any of the discrete status
inputs (e.g. Service Request), if it is also hard wired to the
input NILLCMD the device will respond to a failed checksum
with the selected status bit set and not use the data (i.e. not
write to main memory).
In addition to the signal NVCR (valid command word
received) which may be used to illegalise commands, a signal
NHDR (header word received) is available to the subsystem for
verification of the 1760 message header.
The RT address lines may be continuously monitored or
latched on RESET as required by 1760. If all six RT address
lines go open circuit the store released signal (STREL) will go
high.
A signal is provided to monitor the internal watchdog timers
for test purposes. A set of pins are available to connect
additional external watchdog timers if so desired.
As well as being able to set the Remote Terminal status bits
discretely they may be written to via the VME/MULTIBUS
interface. These status bits as well as the status of the Block
Transfer Logic and Self Test function may be read back from
the device.
A software write / readable BIT register is available.
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SCDCT2577 REV D
SIGNAL DESCRIPTIONS
LA
(Input with pull up resistor)
Input enables the Latched Address option. Normally the
Remote Terminal address inputs are constantly monitored and
compared with the incoming command word. When enabled
the Remote Terminal address inputs are internally latched
every time the unit is reset. The latched address information is
then compared to the incoming command word. This latched
Remote Terminal address function complies with the
requirements of 1760. If left open circuit the device will
default to the latched address mode,
"0" = RT address inputs are NOT latched
"1" = RT address inputs ARE latched
1553 / 1760 DATA BUS
DATABUS 0
(Bidirectional)
Signal is connected to the positive side of the external data
bus transformers for bus 0.
NDATABUS 0
(Bidirectional)
Signal is connected to the negative side of the external data
bus transformers for bus 0.
DATABUS 1
(Bidirectional)
Signal is connected to the positive side of the external data
bus transformers for bus 1.
VME
(Input with pull up resistor)
Select VME or MULTIBUS subsystem interface. If left open
circuit the device will default to VME mode.
"0" = Multibus mode
"1" = VME mode
NDATABUS 1
(Bidirectional)
Signal is connected to the negative side of the external data
bus transformers for bus 1.
NBIT16
(Input with pull down resistor)
Select 8 or 16 bit subsystem data interface. In 8 bit mode only
the lower 8 bits of the data bus (DATA 0-7) are used for all
data transfers. If left open circuit the device will default to 16
bit mode.
"0" = 16 bit mode
"1" = 8 bit mode
WATCHDOG
(Output)
Signal monitors internal watchdog timer, will go high at the
start of a transmission and remain high for 800 µS. If a new
command is received before the signal times out it will be
reset.
NTXINH 0
(Input with pull up resistor)
Input to inhibit transmissions onto channel 0 of the 1553 data
bus. External watchdog timer would be connected to this
input. May be left open circuit if not used.
"0" = Inhibit
"1" = Enable
WRAPEN
(Input with pull down resistor)
Select Remote Terminal wrap around to subaddress 1E. For
this test to work correctly the unit must be in RT mode. The
Bus Controller sends data to subaddress 1E. The data received
is stored in the “transmit” area of the main RAM and the
Command word is stored in the Command / Status memory as
described in BC to RT transfer. The device will respond with
status. The Bus Controller will then send a transmit command
to subaddress 1E and the data contained in the “transmit” area
of the main RAM will be transmitted following the status and
the Command word which is stored in the Command / Status
memory as described in RT to BC transfer.
"0" = Normal mode
"1" = Wrap Around mode
NTXINH 1
(Input with pull up resistor)
Input to inhibit transmissions onto channel 1 of the 1553 data
bus. External watchdog timer would be connected to this
input. May be left open circuit if not used.
"0" = Inhibit
"1" = Enable
SELEN 0
(Output)
Output high indicates that the last command received by the
Remote Terminal was on channel 0 of the 1553 data bus or
channel 0 has been selected by the Bus Controller. Used to
select watchdog timer channel.
MCAIR
(Input with pull down resistor)
This signal sets the unit to respond with a status word within
4 µS (dead bus time) while in Remote Terminal mode.
Subaddress 1F is also enabled to be a valid subaddress for
data. Normally subaddress 00 and 1F are reserved for mode
codes.
"1" = 4 µS dead bus response time, subaddress 1F used for
data.
"0" = 12 µS response time, subaddress 1F used for mode
codes.
SELEN 1
(Output)
Output high indicates that the last command received by the
Remote Terminal was on channel 1 of the 1553 data bus or
channel 1 has been selected by the Bus Controller. Used to
select watchdog timer channel.
INITWD
(Output)
Output indicates that a transmission onto the selected 1553
data bus is about to commence. Used to initiate an external
watchdog timer. The signal is a 250 nS active low pulse.
NENBTL
(Input with pull up resistor)
Signal to enable the Block Transfer Logic. When active a 32
word RAM is inserted as a buffer between the main RAM and
the subsystem. This memory guarantees data consistency by
bursting a message from the BTL memory to the main
memory (write) or from main memory to BTL memory (read)
uninterrupted. The Block Transfer Logic may be selectively
disabled in software giving the subsystem direct access to the
main RAM.
"0" = Enable Block Transfer Logic
"1" = Disable Block Transfer Logic and software selection.
HARD WIRED
ADDR A-E
(Inputs with pull up resistor)
Remote Terminal address inputs for the unit. ADDR A is the
least significant bit and ADDR E is the most significant bit.
ADDR P
(Input with pull up resistor)
Parity bit for the Remote Terminal address inputs. ADDR P
must be set to ODD parity.
C16MHZ
(Input with pull up resistor)
Free running 16 MH
Z
clock input.
SCDCT2577 REV D
3
VME/MULTIBUS INTERFACE
ADIN 0-11
(Inputs with pull up resistor)
12 bit address input to the unit specifying what location the
user will be accessing in the RAM / registers. These address
inputs are inverted when the Multibus interface is selected.
T0-T15
(Output)
16 bit output highway monitors the internal data bus of the
unit. This allows the user to have access to the 1553 data bus
traffic in real time. The user can utilise this bus for message
illegalization and read words such as Command, Data,
Synchronize and Header word (1760 requirement).
DATA 0-15
(Bidirectional IO)
16 bit bidirectional data highway access to internal RAM and
registers. When in 8 bit mode only DATA 0-7 are used. Data
inputs / outputs are inverted when the Multibus interface is
selected.
DISCRETE RT STATUS INPUTS
The following signals are inputs to set the appropriate
bits in the Remote Terminals status word. All inputs are
sampled after NVCR except non mode code receive com-
mands in which case they are sampled after the last data
word has been received. All status inputs are active low.
NME
(Input with pull up resistor)
Message Error, illegalises message. Command will not be
stored in Command / Status memory and no transfers to /
from main RAM will take place. No data will be transmitted
following the status.
UB
(Input with pull up resistor)
Upper byte: When the unit is in 8 bit mode this signal is used
as the LSB of the address lines. In 16 bit mode the signal is
not used and the LSB of the address lines is ADIN 0.
NCARDEN
(Input with pull up resistor)
Signal to indicate the processor is addressing this unit. The
user can use this signal tied to an address decoder to enable
the unit for a read/write operation.
"0" = Enable unit for I/O operations.
NBUSY
(Input with pull up resistor)
Subsystem Busy. No data will be transferred to / from main
RAM and no data will be transmitted following status.
NRD
(Input with pull up resistor)
VME Mode: Data Strobe for a data transfer.
"0" = Write / Read data to/from the subsystem.
"1" = Tristate the Data 0-15 bus.
Multibus Mode: Read strobe for a data transfer.
"0" = Read data from the unit to the subsystem.
"1" = Tristate the Data 0-15 bus.
NTF
(Input with pull up resistor)
Terminal Flag.
NSR
(Input with pull up resistor)
Service Request.
NSSFLAG
(Input with pull up resistor)
Subsystem Flag.
NWR
(Input with pull up resistor)
VME Mode: Write / Read direction flag for NRD data strobe.
"0" = Write data from subsystem to device.
"1" = Read data from device to subsystem.
Multibus Mode: Write strobe for a data transfer.
"0" = Write data from subsystem to device.
"1" = Tristate the Data 0-15 bus.
NDBCA
(Input with pull up resistor)
Dynamic Bus Control Acceptance.
RT DISCRETE SIGNALS
NRES
(Bidirectional IO with pull up resistor)
Bidirectional reset pin. Interface to this pin should be in the
form of an open collector pull down driver. The unit will be
reset when a low level input is asserted on power up. The pin
is bidirectional in that the unit will drive the signal out low
after the status response of the mode code Reset Remote
Terminal. Upon reset the unit will initialise to RT mode and
will be able to respond immediately after the rising edge of
NRES.
NACK
(Open drain output)
After a write / read cycle has begun, this signal indicates that
the write / read operation to the unit has been acknowledged
and that access has been granted. Read data is available and
write data is complete. The user can complete the write / read
cycle.
"0" = Cycle is acknowledged, access granted.
"1" = No acknowledge, wait.
NEMPTY
(Output)
Empty flag for the Command / Status FIFO memory which
can store up to 32 command words (RT) or 32 status words
(BC). In RT mode the memory will store all command words
that have accessed the main RAM. This includes all standard
commands to receive and transmit data from the main RAM
and mode codes with data that require subsystem involvement
ie. Synchronize With Data and Transmit Vector Word. In BC
mode all status responses are stored in this memory. Access to
this memory is gained by reading from address 0 00 00.
"0" = Memory is empty, no words to read.
"1" = Memory is not empty, has words to read.
NILLCMD
(Input with pull up resistor)
Input to illegalise a command to the Remote Terminal with a
clear status response. The signal is sampled after NVCR
except non mode code receive commands in which case it is
sampled after the last data word has been received. A low on
this input will illegalise the message, Command will not be
stored in the Command / Status memory and no transfers to /
from main RAM will take place. The device will respond with
a clear status unless a bit has been specifically set. No data
will be transmitted following status.
INHMC
(Input with pull down resistor)
Inhibit Mode Code: subaddress 00 and 1F are treated as
normal non mode code transmit or receive commands. For use
in RT mode only. May be left open circuit for normal
operation.
"0" = Normal operation.
"1" = Inhibit all mode codes.
NFULL
(Output)
Full flag for the Command / Status FIFO memory. When the
signal goes low the memory is full and will not store any more
data.
SCDCT2577 REV D
4
NVCR
(Output)
Early indication that the Remote Terminal has received a
command and the command word is available on T0-T15.
This can be used for message illegalization.
ERROR
(Output)
Indication that an error has occurred either in the information
transferred to the unit from the subsystem or in the transfers
on the 1553 data bus. Nature of error is available by reading
from register location 0 00 12.
NDATA
(Output)
Access to valid data word in real time before being written to
RAM. Data word available on T0-T15 during active low
signal.
NSTSTRB
(Output)
This signal goes low for 8.5 µS to indicate a valid transfer has
been completed on the 1553 data bus and the received Status
word is now available on the T0-T15 highway. The Status
word is also stored in the Command / Status memory at this
time. Once the signal goes high data received by the Bus
Controller (RT to BC transfer) will be transferred to the main
RAM from the 32 word data buffer memory. Note: Data
transferred in RT to RT transfers is not stored in the Bus
Controllers main RAM.
NCMDSTRB
(Output)
This signal indicates that a completely validated message has
been received for standard subaddress data activity. Mode
commands with or without data will not generate this signal.
The NCMDSTRB signal is 8.5 µS long and is an indication
that a DMA burst will initiate at the end of NCMDSTRB to
transfer words between the 32 word data memory and the
internal main RAM. All subsystem read / writes to the main
RAM that have been acknowledged (NACK = "0") before
NCMDSTRB has begun must now be completed within 8.5
µS. All subsystem read / write requests to the main RAM
initiated after NCMDSTRB has begun will be held off (no
acknowledge) until the DMA cycle has been completed. The
length of the DMA cycle is dependant on the number of
words to DMA into RAM. Access to the 32 word BTL
memory is still possible during the DMA cycle by the
subsystem. However, transfers between the BTL memory and
the main RAM will be locked out..
NINHST
(Input with pull up resistor)
May be used to illegalise a message just received. Signal can
be tied to STATUS for illegalization due to 1760 checksum
failures. A low will prevent any data received being
transferred to the main RAM, and the Status word will not be
stored in the Command / Status memory.
1760 SIGNALS
NENCHK
(Input with pull up resistor)
Enables / disables the internal hardware checksum generation
and validation for both Remote Terminal and Bus Controller.
When enabled, the circuitry will check all incoming data for
correct checksum and generate the correct checksum word for
an outgoing data transfer.
"0" = Enable checksum circuitry.
"1" = Disable checksum circuitry.
BCST
(Output)
Output high indicates command received was a broadcast.
Signal will remain high until next command is received.
MCDET
(Output)
Output high indicates command received was a mode
command. Signal will remain high until next command is
received.
STATUS
(Open drain output)
Open drain output will toggle high or low on each incoming
data word from the 1553 data bus provided NENCHK is
enabled. When the last data word is received the STATUS line
is sampled by the protocol circuitry to determine if the
checksum for the message is valid. At the end of the message,
if STATUS is low then the checksum is not valid. This
STATUS signal can be wired to several different pins to
customise the units response to a checksum failure. STATUS
can be wired to signals such as NILLCMD and NSR which
would cause the message to be illegalised and set Service
Request bit in the Status.
NSYNC
(Output)
Signal to subsystem indicating receipt of a Synchronize mode
commands If the mode code has an associated data word, it
will be available on T0-T15 at this time. If there is no
associated data word, T0-T15 will be zero.
BC DISCRETE SIGNALS
NNEWBUS
(Input with pull up resistor)
A Bus Control sequence may not normally be initiated until
the current sequence is completed, indicated by signal EOT.
However, the Bus Control sequence may be terminated and
restarted if NNEWBUS is active low along with write to
address 0 00 00. This feature would only be used in bus
switching.
NVALCHK
(Output)
Latched version of the STATUS signal. NVALCHK is latched
on the falling edge of NCMDSTRB (RT) or NSTSTRB (BC)
and will remain stable until the next NCMDSTRB or
NSTSTRB.
"0" = Checksum word was not valid.
"1" = Checksum word was valid.
EOT
(Output)
Valid transfer on 1553 data bus selected has been completed.
"0" = Transfer in progress.
"1" = Transfer complete.
NHDR
(Output)
In Mil-Std-1760, the first data word of a message is defined as
a Header word. The NHDR signal indicates the presence of
the Header word on the T0-T15 highway as it is received. The
user can also read the Header word from RAM.
NDBC
(Output)
Active low indicates that the command received by the
Remote Terminal was mode code Dynamic Bus Control.
Signal will remain low until next command is received.
STREL
(Output)
When the store is released from the aircraft all the Remote
Terminal address inputs go high causing signal STREL to go
high.
BCNRT
(Output)
Indicates what mode the unit is in.
"0" = Remote Terminal.
"1" = Bus Controller.
SCDCT2577 REV D
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