IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
IDTCV132B
ADVANCE
INFORMATION
FEATURES:
•
•
•
•
•
•
•
•
•
•
3 PLL architecture
USB48 has 180° phase difference from DOT48 and VCH
3V66 lead PCI 1.5ns to 3.5ns
Band-gap circuit for differential output
High power-noise rejection ratio
100MHz to 200MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write
All CPU-Stop and PCI-Stop related functions are removed
Available in SSOP package
IDTCV132B is a 56 pin clock device for Intel springdale chip set and for Intel
advance P4 processors. This device also implements Band-gap referenced
I
REF
to reduce the impact of V
DD
variation on differential outputs, which can
provide more robust system performance.
DESCRIPTION:
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 125ps
• PCI CLK cycle to cycle jitter < 250ps
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
CPU CLK
Output Buffers
CPU[2:0]
XTAL_IN
XTAL
Osc Amp
I
REF
REF 1.0
XTAL_OUT
SDATA
SCLK
SM Bus
Controller
PLL2
SSC
3V66/PCI
Output Buffers
PCI[6:0], PCIF[2:0]
3V66[4:0]
SRC
V
TT_PWRGD
Watch Dog
Timer
FSA,B
Control
Logic
DOT48/USB48
P
WRDWN
#
PLL3
48MHz
Output Buffer
VCH
OUTPUT TABLE
CPU (Pair)
3
3V66
4
3V66/VCH
1
PCI
7
PCIF
3
REF
2
48MHz
2
SRC (Pair)
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
JANUARY 2005
DSC 6546/1
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
REF0
REF1
V
DD
_REF
XTAL_IN
XTAL_OUT
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
FSB
V
DDA
V
SSA
V
SS_
IREF
IREF
FSA
NC
NC
V
DD_
CPU
CPU2
CPU2#
V
SS_
CPU
CPU1
CPU1#
V
SS
_REF
PCIF0
PCIF1
PCIF2
V
DD_
PCI
V
SS_
PCI
PCI0
PCI1
PCI2
PCI3
V
DD_
CPU
CPU0
CPU0#
V
DD_
PCI
V
SS_
PCI
PCI4
PCI5
PCI6
V
SS_
SRC
SRC
SRC#
V
DD_
SRC
V
TT
_P
WRGD
#
V
DD_
48
V
SS_
48
DOT_48
USB_48
SDA
3V66_3/VCH
PWRDWN#
3V66_0
3V66_1
V
DD_
3V66
V
SS_
3V66
3V66_2
3V66_3
SCL
SSOP
TOP VIEW
HW FREQUENCY SELECTION
FSA
0
0
0
1
1
1
FSB
0
MID
1
0
1
MID
CPU
100
REF/N
200
133
166
Hi-Z
SRC
100
REF/N
100
100
100
Hi-Z
3V66
66
REF/N
66
66
66
Hi-Z
PCI/F
33
REF/N
33
33
33
Hi-Z
REF0
14.318
REF
14.318
14.318
14.318
Hi-Z
REF1
14.318
REF
14.318
14.318
14.318
Hi-Z
USB/DOT
48
REF/N
48
48
48
Hi-Z
2
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
REF0
REF1
V
DD
_REF
XTAL_IN
XTAL_OUT
V
SS
_REF
PCIF0
PCIF1
PCIF2
V
DD
_PCI
V
SS
_PCI
PCI0
PCI1
PCI2
PCI3
V
DD
_PCI
V
SS
_PCI
PCI4
PCI5
PCI6
PWRDWN#
3V66_0
3V66_1
V
DD
_3V66
V
SS
_3V66
3V66_2
3V66_3
SCL
3V66_4/VCH
SDA
USB48
DOT48
V
SS
_48
V
DD
_48
V
TT
_P
WRGD
#
V
DD
_SRC
SRC#
SRC
V
SS
_SRC
CPU0#
CPU0
V
DD
_CPU
CPU1#
CPU1
Type
I/O
I/O
PWR
IN
OUT
GND
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
IN
OUT
OUT
PWR
GND
OUT
OUT
IN
GND
I/O
OUT
OUT
GND
PWR
IN
PWR
OUT
OUT
GND
OUT
OUT
PWR
OUT
OUT
Description
14.318 MHz reference clock output
14.318 MHz reference clock output
3.3V
Xtal input
Xtal output
GND
PCI free running clock
PCI free running clock
PCI free running clock
3.3V
GND
GND
PCI clock
PCI clock
PCI clock
3.3V
GND
PCI clock
PCI clock
PCI clock
Power down, low active
66MHz
66MHz
PWR
GND
66MHz
66MHz
SMBus clock
66MHz or 48MHz
SMBus data
48MHz
48MHz
GND
3.3V
Power on assertion to latch FSA, FSB signal. Active LOW.
3.3V
SATA 0.7V current mode differential clock output
SATA 0.7V current mode differential clock output
GND
Used for power on latch, active HIGH. After power on, becomes power down control, active
LOW.
Used for power on latch, active LOW
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
45
46
47
48
49
50
51
52
53
54
55
56
Name
V
SS
_CPU
CPU2#
CPU2
V
DD
_CPU
NC
NC
FSA
IREF
V
SS
_IREF
V
SSA
V
DDA
FSB
Type
GND
OUT
OUT
PWR
Description
GND
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
No Connection
No Connection
CPU frequency select, latched at V
TT
_P
WRGD
# assertion
Differential reference current
Host 0.7V current mode differential clock output
Analog V
SS
Analog V
DD
GND
IN
OUT
GND
GND
PWR
IN
SM BUS PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Start
D2h
Acknowledge
Register offset byte (starting byte)
Acknowledge
Byte count N (0 is not a valid byte count)
Acknowledge
First data byte
Acknowledge
Second data byte
Acknowledge
:
Nth data byte
Stop
Description
INDEX BLOCK READ PROTOCOL
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Slave
Master
Slave
Start
D2h
Acknowledge
Register offset byte (starting byte)
Acknowledge
Repeated start
D3h
Acknowledge
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
Acknowledge
Offset data byte, specified by bit 11-18
Acknowledge
Offset + 1 data byte
:
Offset + N-2
Acknowledge
Offset + N-1
Not acknowledge
Stop
Description
4
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 0
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FSB read back
FSA read back
Description/Function
0
1
Type
R
R
R
R
R
R
R
R
Power On
0
0
0
0
0
0
BYTE 1
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
SRC
SRC
Reserved
Reserved
Reserved
CPU2
CPU1
CPU0
Output Enable
Output Enable
Output Enable
Tristate
Tristate
Tristate
Enable
Enable
Enable
RW
RW
RW
Description/Function
SRC free run control by Byte 3, bit 7
Output Enable
0
Free Run
Tristate
1
Stoppable
Enable
Type
RW
RW
Power On
0
1
1
1
1
1
1
1
BYTE 2
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
SRC_P
WRDWN
drive mode
SRC Stop mode
CPU2_P
WRDWN
drive mode
CPU1_P
WRDWN
drive mode
CPU0_P
WRDWN
drive mode
Reserved
Reserved
Reserved
Description/Function
0
Driven
Driven
Driven
Driven
Driven
1
Tristate
Tristate
Tristate
Tristate
Tristate
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
BYTE 3
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
PCI and SRC Stop
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Description/Function
Stop PCI and SRC,
doesn't include free run
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
5
0
Stop
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
1
Normal
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
