CXK77B1810AGB
-5/6
High Speed Bi-CMOS Synchronous Static RAM
Description
The CXK77B1810AGB-5/6 is a high speed 1M bit
Bi-CMOS synchronous static RAM organized as
65536 words by 18 bits. This SRAM integrates input
registers, high speed SRAM and write buffer onto a
single monolithic IC and features the delayed write
system to reduce the dead cycles.
Features
•
Fast cycle time
CXK77B1810AGB-5
Preliminary
119 pin BGA (Plastic)
(Cycle)
5ns
(Frequency)
200MHz
-6
6ns
167MHz
•
Inputs and outputs are GTL/HSTL compatible
•
Controlled Impedance Driver
•
•
•
•
•
•
Single 3.3V power supply: 3.3V±0.15V
Byte-write possible
OE asynchronization
JTAG test circuit
Package 119TBGA
4 kinds of synchronous operation mode
Register-Register mode (R-R mode)
Register-Flow Thru mode (R-F mode)
Register-Latch mode (R-L mode)
Dual clock mode (D-C mode)
Function
65536 word x 18bit High Speed Bi-CMOS Synchronous SRAM
Structure
Silicon gate Bi-CMOS IC
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96811
CXK77B1810AGB
Block Diagram
16
A0 to 15
Input
Reg.
2:1
Mux
Add.
Dout
2:1
Mux
Write
Store
Reg.
64K
×
18
Din
Write
pulse
Output
latch
DQ
Reg.
Read
Comp.
S
Reg.
W
Reg.
Self
Time
Write
Logic
2
BW
a to b
Reg.
K/K
C/C
Output
Clock
M1
M2
Mode
Control
G
–2–
CXK77B1810AGB
Pin Configuration
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
Q
NC
NC
DQb
NC
V
DD
Q
NC
DQb
V
DD
Q
NC
DQb
V
DD
Q
DQb
NC
NC
NC
V
DD
Q
2
A
NC
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQb
A
A
TMS
3
A
NC
A
V
SS
V
SS
V
SS
BWb
V
SS
VREF
V
SS
V
SS
V
SS
V
SS
V
SS
M1
A
TDI
4
NC
NC
V
DD
ZQ
S
G
C
C
V
DD
K
K
W
A
A
V
DD
NC
TCK
5
A
NC
A
V
SS
V
SS
V
SS
V
SS
V
SS
VREF
V
SS
BWa
V
SS
V
SS
V
SS
M2
A
TDO
6
A
NC
A
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DD
Q
NC
NC
NC
DQa
V
DD
Q
DQa
NC
V
DD
Q
DQa
NC
V
DD
Q
NC
DQa
NC
ZZ
V
DD
Q
Pin Description
Symbol
A
DQx
K
K
C
C
VREF
Description
Address Input
Data I/O in byte
(a to b)
Positive Clock
Negative Clock
Symbol
BWX
S
G
ZZ
Description
Byte Write Enable
(a to b)
Chip Select
Asyn Output Enable
Sleep Mode Select
JTAG Clock
JTAG Mode Select
JTAG Data In
Symbol
V
DD
V
DD
Q
V
SS
M1, M2
ZQ
NC
Description
+3.3V power supply
Output power supply
Ground
Mode Select
Output Impedance
Control
No Connect
Output Positive Clock(
∗
) TCK
Output Negative
Clock(
∗
)
Input Reference
TMS
TDI
Write Enable
JTAG Data Out
TDO
W
(
∗
) These pins should be tied to V
DD
or V
SS
except D-C mode.
–3–
CXK77B1810AGB
Package Outline
Unit: mm
119 TER M I AL BG A(
N
PLASTI )
C
14.
0
11.
5
B
A
X
0. 0. 1
6}
C
3.
19
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
7.
62
1.
27
84
0.
5
19.
1.
0
3-
C
~4
0.
10
1 2 3 4 5 6 7
0. 0. 1
6}
1.
5
0. 75}0. 15
0. 3
0. 1
C
A
B
0.
15 C
D ETAI X
L
PAC KAG E STR U C TU R E
PAC KAG E M ATER I
AL
EPO XY R ESI
N
C O PPER - LAD LAM I ATE
C
N
SO LD ER
0.
8g
SO N Y C O D E
EI C O D E
AJ
JED EC C O D E
BG A-
119P-
01
BO AR D M ATER I
AL
TER M I AL M ATER I
N
AL
PAC KAG E W EI H T
G
–4–
32
20.
0
22.
0.
35 C
27
1.
C
4-
6
0.
C
5
1.
