SONY
®
Σ
RAM
Description
CXK79M72C160GB
CXK79M36C160GB
CXK79M18C160GB
33/4/44
Preliminary
16Mb 1x1Lp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36 or 1Mb x 18)
The CXK79M72C160GB (organized as 262,144 words by 72 bits), CXK79M36C160GB (organized as 524,288 words by 36
bits), and the CXK79M18C160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs
with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined
for SigmaRAMs. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single
monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Late Write (LW) write operations are supported,
providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-
synchronous operation.
All address and control input signals are registered on the rising edge of the CK differential input clock.
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control
signals are registered.
During write operations, input data is registered once, on the rising edge of CK, one full cycle after the address and control
signals are registered.
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor
RQ is connected between ZQ and V
SS
, the impedance of the SRAM’s output drivers is set to ~RQ/5.
300 MHz operation (300 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
Features
•
3 Speed Bins
-33
-4
-44
Cycle Time / Data Access Time
3.3ns / 1.8ns
4.0ns / 2.1ns
4.4ns / 2.3ns
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 1.8V power supply (V
DD
): 1.7V (min) to 1.95V (max)
Dedicated output supply voltage (V
DDQ
): 1.8V or 1.5V typical
HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): V
DDQ
/2 typical
Common I/O
Single Data Rate (SDR) data transfers
Pipelined (PL) read operations
Late Write (LW) write operations
Burst capability with internally controlled Linear Burst address sequencing
Burst length of two, three, or four, with automatic address wrap
Full read/write data coherency
Byte write capability
Two cycle deselect
Differential input clocks (CK/CK)
Data-referenced output clocks (CQ/CQ)
Programmable output driver impedance via dedicated control pin (ZQ)
Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)
JTAG boundary scan (subset of IEEE standard 1149.1)
209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb 1x1Lp, HSTL, rev 0.1
1 / 27
July 6, 2001
SONY
®
Σ
RAM
CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
256Kb x 72 Pin Assignment (Top View)
Preliminary
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
CQ
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQd
2
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
DQc
CQ
DQh
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
3
A
BWc
BWh
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
TMS
4
E2
BWg
BWd
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDI
5
A
(16M)
NC
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
A1
A0
7
A
(8M)
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
A
A
8
E3
BWb
BWe
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDO
9
A
BWf
BWa
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
TCK
10
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
DQf
CQ
DQa
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
CQ
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQe
16Mb 1x1Lp, HSTL, rev 0.1
2 / 27
July 6, 2001
SONY
®
Σ
RAM
CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
512Kb x 36 Pin Assignment (Top View)
Preliminary
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
NC
NC
NC
NC
NC
DQc
DQc
DQc
DQc
CQ
NC
NC
NC
NC
DQd
DQd
DQd
DQd
DQd
2
NC
NC
NC
NC
DQc
DQc
DQc
DQc
DQc
CQ
NC
NC
NC
NC
NC
DQd
DQd
DQd
DQd
3
A
BWc
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
TMS
4
E2
NC
BWd
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDI
5
A
(16M)
A
(x36)
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
A1
A0
7
A
(8M)
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
A
A
8
E3
BWb
NC
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDO
9
A
NC
BWa
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
TCK
10
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
CQ
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
11
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
CQ
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
16Mb 1x1Lp, HSTL, rev 0.1
3 / 27
July 6, 2001
SONY
®
Σ
RAM
CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
1Mb x 18 Pin Assignment (Top View)
Preliminary
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
A
BWb
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(2M)
TMS
4
E2
NC
NC
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDI
5
A
(16M)
A
(x36)
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
MCH
MCL
V
DD
MCL
A
A1
A0
7
A
(8M)
A
A
(x18)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
A
A
8
E3
NC
NC
V
REF
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
REF
A
A
TDO
9
A
NC
BWa
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
(4M)
TCK
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
16Mb 1x1Lp, HSTL, rev 0.1
4 / 27
July 6, 2001
SONY
®
Σ
RAM
CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Pin Description
Preliminary
Symbol
A
A1, A0
DQa, DQb
DQc, DQd
DQe, DQf
DQg, DQh
Type
Input
Input
I/O
Description
Address Inputs - Registered on the rising edge of CK.
Address Inputs 1,0 - Registered on the rising edge of CK. Initialize burst counter.
Data Inputs / Outputs - Registered on the rising edge of CK during write operations. Driven from
the rising edge of CK during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
DQe - indicates Data Byte e
DQf - indicates Data Byte f
DQg - indicates Data Byte g
DQh - indicates Data Byte h
Differential Input Clocks
Output Clocks
Chip Enable Control Input - Registered on the rising edge of CK.
E1 = 0 enables the device to accept read and write commands.
E1 = 1 disables the device.
See the Clock Truth Table section for further information.
Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See the Clock
Truth Table and Depth Expansion sections for further information.
Programmable Chip Enable Active-Level Select Inputs - These pins must be tied “high” or
“low” at power-up. See the Clock Truth Table and Depth Expansion sections for further infor-
mation.
Address Advance Control Input - Registered on the rising edge of CK.
ADV = 0 loads a new address and begins a new operation when the device is enabled.
ADV = 1 increments the address and continues the previous operation when the device is
enabled.
See the Clock Truth Table section for further information.
Write Enable Control Input - Registered on the rising edge of CK.
W = 0 specifies a write operation when ADV = 0 and the device is enabled.
W = 1 specifies a read operation when ADV = 0 and the device is enabled.
See the Clock Truth Table section for further information.
Byte Write Enable Control Inputs - Registered on the rising edge of CK.
BWa = 0 specifies write Data Byte a during a write operation
BWb = 0 specifies write Data Byte b during a write operation
BWc = 0 specifies write Data Byte c during a write operation
BWd = 0 specifies write Data Byte d during a write operation
BWe = 0 specifies write Data Byte e during a write operation
BWf = 0 specifies write Data Byte f during a write operation
BWg = 0 specifies write Data Byte g during a write operation
BWh = 0 specifies write Data Byte h during a write operation
See the Clock Truth Table section for further information.
Operation Protocol Control Inputs - These pins must be tied “high”, “high”, and “low” respec-
tively, at power-up, to select Single Data Rate Pipelined Read / Late Write operation protocol.
Output Impedance Control Resistor Input - This pin must be tied to V
SS
through an external
impedance matching resistor RQ at power-up. Output driver impedance is set to one-fifth the
value of the RQ resistor, nominally.
See the Output Driver Impedance Control section for further information.
CK, CK
CQ, CQ
E1
Input
Output
Input
E2, E3
EP2, EP3
Input
Input
ADV
Input
W
Input
BWa, BWb
BWc, BWd
BWe, BWf
BWg, BWh
Input
M2, M3, M4
ZQ
Input
Input
16Mb 1x1Lp, HSTL, rev 0.1
5 / 27
July 6, 2001
