CXP888P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP888P60 is a CMOS 8-bit micro-computer
which consists of A/D converter, serial interface,
timer/counter, time base timer, high precision timing
pattern generation circuits, PWM output, VISS/
VASS circuit, 32kHz timer/counter, remote control
receiving circuit, VSYNC separator and the
measurement circuit which measure signals of
capstan FG amplifier and drum FG/PG amplifier and
other servo systems, as well as basic configurations
like 8-bit CPU, PROM, RAM and I/O port. They are
integrated into a single chip.
Also, CXP888P60 provides sleep/stop function
which enables to lower power consumption.
The CXP888P60 is the PROM-incorporated
version of the CXP88860 with built-in mask ROM.
This provides the additional feature of being able to
write directly into the program. Thus, it is most
suitable for evaluation use during system
development and for small-quantity production.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
•
A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
•
Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
•
Incorporated PROM capacity 60K bytes
•
Incorporated RAM capacity
1600 bytes (including PPG RAM)
•
Peripheral function
— A/D converter
8 bits, 8 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time base timer
32kHz timer/counter
— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel
5-bit, 8-satge FIFO (RECCTL control), 1channel
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 2 channels
— Analog signal input circuit
Capstan FG amplifier circuit
Drum FG amplifier circuit
Drum PG amplifier circuit
PBCTL amplifier circuit
— CTL write/rewrite circuit
Recording current control circuit
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1 channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output
PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
•
Interruption
20 factors, 15 vectors, multi-interruption possible
•
Standby mode
SLEEP/STOP
•
Package
100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96107-ST
Block Diagram
AV
REF
AVss
INT0
INT1/NMI
INT2
EXTAL
XTAL
TEX
TX
RST
MP
V
DD
Vss
Vpp
AV
DD
2
PORT A
AN0 to AN13
8
PA0 to PA7
SPC700
CPU CORE
PORT B
14
CLOCK
GENERATOR/
SYSTEM CONTROL
8
PB0 to PB7
A/D CONVERTER
2
NMI
CS0
SI0
SO0
SCK0
FIFO
SERIAL
INTERFACE UNIT
(CH0)
EC
8 BIT TIMER/COUNTER 0
INTERRUPT CONTROLLER
2
PROM
60K BYTES
RAM
1600 BYTES
PORT C
SI1
SO1
SCK1
8
SERIAL INTERFACE UNIT
(CH1)
PC0 to PC7
TO
SYNC
2
2
PRESCALER/
TIME BASE TIMER
3
FIFO
FRC
CAPTURE UNIT
FIFO
PORT E
V SYNC SEPARATOR
PORT D
EC
SELECT
8 BIT TIMER/COUNTER1
8
PD0 to PD7
4
4
PORT F
PE0, 1, 6, 7
PE2 to PE5
4
4
PF0 to PF3
PF4 to PF7
EXI0
EXI1
SERVO INPUT
CONTROL
CFG
DFG
DPG
CTLAMP
GAIN
CONTROL
AMP
32kHz
TIMER/COUNTER
PWM
14 BIT PWM GENERATOR
2
2
PROGRAMABLE
PATTERN
GENERATOR
RAM
CH0
REALTIME PULSE
GENERATOR
CH1
FIFO
5
PORT I
PORT H
DDO
VISS/VASS
PULSE WIDTH
COUNTER
PORT G
AMPV
DD
AMPV
SS
PPO0 to PPO18
RTO3 to RTO7
–2–
4
19
5
RMC
REMOCON INPUT
2
PG0, 1
8
PH0 to PH7
PWM0
DAA0
12 BIT PWM GENERATOR CH0
8
PI0 to PI7
PWM1
DAA1
12 BIT PWM GENERATOR CH1
HGO
PSEUDO HSYNC GENERATOR
2
ADJ
RECCTL
CTLCIN
CTL R/W CONTROL
CXP888P60
CXP888P60
Pin Assignment
(Top View)
PA0/PPO0/HGO
PB6/PPO14
PB7/PPO15
PA1/PPO1
PE3/SYNC
PA7/PPO7
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PE0/SCK1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10
PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16
PI7
PI6
PI5
PI4
PI3
PI2
PI1/EC/INT2
PI0/INT0/ENV-DET
PD7/SI0
PD6/SO0
PD5/SCK0
PD4/CS0
PD3/TO/DDO/ADJ/SRVO
PD2/PWM
PD1/RMC
PD0/INT1/NMI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE5/EXI1
PE6/PWM0/DAA0
PE7/PWM1/DAA1
CFG
DFG
DPG
VREFOUT
AMPV
SS
CTLSAMPI
CTLFAMPO
CTLAG
CTLAMP (+)
CTLAMP (–)
CTLCIN (–)
CTLCIN (+)
RECCTL (+)
RECCTL (–)
AMPV
DD
RECCAP
V
DD
AN0/ANOUT
AN1
AN2
AN3
PF0/AN4
PF1/AN5
AV
DD
AV
REF
AV
SS
PF2/AN6
PH5
PG1/AN13
PG0/AN12
PF7/AN11
PF6/AN10
PH7
PH6
EXTAL
XTAL
RST
PH2
PH1
PH0
V
SS
MP
PE2/SI1
Note)
1. Vpp (Pin 90) is always connected to V
DD
.
2. V
DD
(Pins 61 and 89) are both connected to V
DD
3. Vss (Pins 41 and 88) are both connected to GND.
4. MP (Pin 39) must be connected to GND.
–3–
PF5/AN9
PF4/AN8
PF3/AN7
PH4
PH3
PE4/EXI0
Vpp
V
DD
V
SS
TX
TEX
PE1/SO1
CXP888P60
Pin Description
Symbol
PA0/PPO0
/HGO
PA1/PPO1
to
PA7/PPO7
I/O
Output/Real-time
output/Output
Output/
Real-time output
(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)
Description
Pseudo HSYNC output pin.
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
Programmable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
(19 pins)
PA0 can be tri-state controlled with PPG.
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
PD0/INT1/
NMI
PD1/RMC
PD2/PWM
PD3 /TO
DDO/ADJ
SRVO
PD4/CS0
PD5/SCK0
PD6/SO0
PD7/SI0
PE0/SCK1
PE1/SO1
PE2/SI1
PE3/SYNC
PE4/EXI0
PE5/EXI1
PE6/PWM0/
DAA0
PE7/PWM1/
DAA1
I/O/
Real-time output
I/O/
Real-time output
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
(5 pins)
Input pin to request external interruption
and non-maskable interruption.
Remote control receiving circuit input pin.
14-bit PWM output pin.
Timer/counter, CTL duty detector, 32kHz
oscillation adjustment and servo amplifier
output pin.
Serial chip select (CH0) input pin.
Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial clock (CH1) I/O pin
Serial data (CH1) output pin
Serial data (CH1) input pin
I/O/Input/Input
I/O/Input
I/O/Output
I/O/Output/Output/ (Port D)
8-bit I/O port. I/O can be
Output/Output
set in a unit of single bits.
(8 pins)
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
Output/I/O
Output/Output
Input/Input
Input/Input
Input/Input
Input/Input
Output/Output
Output/Output
–4–
(Port E)
8-bit port. Bits 2, 3, 4 and 5 Composite sync signal input pin.
are for inputs; bits 0, 1, 6
and 7 are for outputs.
External input pin for FRC capture unit.
(8 pins)
(2 pins)
DA gate pulse
output pin.
(2 pins)
PWM output pin.
(2 pins)
CXP888P60
Description
AN0/ANOUT
AN1 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
PG0/AN12
PG1/AN13
I/O
Input/Output
Input
Input/Input
Description
Analog circuit internal
waveform output pin.
Output/Input
(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)
(Port G)
2-bit input port.
(2 pins)
Analog input pin for
A/D converter.
(14 pins)
Input/Input
PH0 to PH7
Output
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
(Port I)
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)
Input pin to request
Trigger pulse input
external interruption.
pin for head
Active when falling
switching.
edge.
Input pin to request
External event input external interruption.
pin for timer/counter. Active when falling
edge.
PI0/INT0/
ENV-DET
I/O/Input
PI1/EC/
INT2
PI2 to PI7
CFG
DFG
DPG
RECCTL (+)
RECCTL (–)
CTLCIN (+)
CTLCIN (–)
CTLAMP (+)
CTLAMP(–)
CTLFAMPO
CTLSAMPI
RECCAP
VREFOUT
CTLAG
AMPV
SS
AMPV
DD
I/O/Input/Input
I/O
Input
Input
Input
I/O
Output
Input
Output
Input
I/O
Output
Output
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
RECCTL signal output pin.
(2 pins)
PBCTL signal input pin.
(2 pins)
Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)
Input PBCTL signal with capacitor coupled.
(2 pins)
PBCTL signal 1st amplifier output.
PBCTL signal 2nd amplifier input.
Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.
Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.
Capacitor connecting pin for the CTL and AGND smoothing.
Analog signal input circuit GND pin.
Analog signal input circuit power supply pin.
–5–
