CY14E256LA
256 Kbit (32K x 8) nvSRAM
Features
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Functional Description
The Cypress CY14E256LA is a fast static RAM, with a nonvol-
atile element in each memory cell. The memory is organized as
32K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
25 ns and 45 ns Access Times
Internally Organized as 32K x 8 (CY14E256LA)
Hands off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Infinite Read, Write, and Recall Cycles
1 Million STORE Cycles to QuantumTrap
20 year Data Retention
Single 5V +10% Operation
Industrial Temperature
44-Pin TSOP - II and 32-Pin SOIC Package
Pb-free and RoHS compliance
Cypress Semiconductor Corporation
Document Number: 001-54952 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 08, 2009
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CY14E256LA
Contents
Features ...............................................................................1
Functional Description .......................................................1
Contents ..............................................................................2
Pinouts ................................................................................3
Device Operation ................................................................4
SRAM Read .........................................................................4
SRAM Write .........................................................................4
AutoStore Operation ..........................................................4
Hardware STORE Operation ..............................................4
Hardware RECALL (Power Up) ..........................................5
Software STORE .................................................................5
Software RECALL ...............................................................5
Preventing AutoStore .........................................................6
Data Protection ...................................................................6
Noise Considerations .........................................................6
Best Practices .....................................................................7
Maximum Ratings ...............................................................8
Operating Range .................................................................8
DC Electrical Characteristics ............................................ 8
AC Test Conditions ............................................................ 9
Data Retention and Endurance ......................................... 9
Capacitance ........................................................................ 9
Thermal Resistance ............................................................ 9
AC Switching Characteristics .........................................10
AutoStore/Power Up RECALL .........................................12
Software Controlled STORE/RECALL Cycle ..................13
Hardware STORE Cycle ...................................................14
Switching Waveforms ......................................................14
Truth Table For SRAM Operations ..................................15
Part Numbering Nomenclature ........................................15
Ordering Information ........................................................16
Package Diagram ..............................................................17
Document History Page ...................................................18
Sales, Solutions, and Legal Information ........................18
Worldwide Sales and Design Support .........................18
Products ......................................................................18
Document Number: 001-54952 Rev. *B
Page 2
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CY14E256LA
Pinouts
Figure 1. Pin Diagram - 44 Pin TSOP II/32 Pin SOIC
NC
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[4]
NC
[3]
NC
[2]
NC
NC
[1]
[1]
NC
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
44 - TSOP II
(x8)
32 - SOIC
(x8)
Top View
(not to scale)
Top View
(not to scale)
Table 1. Pin Definitions
Pin Name
A
0
– A
14
WE
CE
OE
V
SS
V
CC
HSB
I/O Type
Input
Input
Input
Input
Ground
Power
Supply
Description
Address Inputs Used to Select One of the 32,768 bytes of the nvSRAM.
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE HIGH.
Ground for the Device.
Must be connected to the ground of the system.
Power Supply Inputs to the Device.
DQ
0
– DQ
7
Input/Output
Bidirectional Data I/O Lines.
Used as input or output lines depending on operation.
Input/Output
Hardware STORE Busy (HSB).
When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
Power
Supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
V
CAP
NC
No Connect
No Connect.
This pin is not connected to the die.
Notes
1. Address expansion for 1 Mbit. NC pin not connected to die
2. Address expansion for 2 Mbit. NC pin not connected to die.
3. Address expansion for 4 Mbit. NC pin not connected to die.
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Document Number: 001-54952 Rev. *B
Page 3
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CY14E256LA
Device Operation
The CY14E256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14E256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the
Truth Table For SRAM Operations
on page 15 for a
complete description of read and write modes.
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to
DC Electrical
Characteristics
on page 8 for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. Place a
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
V
CC
SRAM Read
The CY14E256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A
0-14
determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of t
AA
(read cycle 1). If the read
is initiated by CE or OE, the outputs are valid at t
ACE
or at t
DOE
,
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the t
AA
access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
0.1uF
10kOhm
V
CC
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–7
are
written into the memory if the data is valid t
SD
before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers t
HZWE
after WE goes LOW.
WE
V
CAP
V
CAP
V
SS
AutoStore Operation
The CY14E256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14E256LA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
AutoStore
on page 6. In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
Hardware STORE Operation
The CY14E256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E256LA conditionally initiates a STORE
operation after t
DELAY
. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
DELAY
) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14E256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
Document Number: 001-54952 Rev. *B
Page 4
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CY14E256LA
During any STORE operation, regardless of how it is initiated,
the CY14E256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the CY14E256LA remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
STORE
cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
During this time, HSB is driven low by the HSB driver.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14E256LA Software
STORE cycle is initiated by executing sequential CE controlled
read cycles from six specific address locations in exact order.
During the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the nonvolatile
elements. After a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0FC0 Initiate STORE Cycle
Table 2. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE
X
L
X
L
A
14
- A
0
[6]
X
X
X
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
Output High-Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Power
Standby
Active
Active
Active
[7]
Notes
6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54952 Rev. *B
Page 5
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