CY14B116K/CY14B116M
16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with
Real Time Clock
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
❐
25-ns and 45-ns access times
❐
Internally organized as 2048 K × 8 (CY14B116K),
1024 K × 16 (CY14B116M)
❐
Hands-off automatic STORE on power-down with only a
small capacitor
❐
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
❐
RECALL to SRAM initiated by software or power-up
■
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
Data retention: 20 years
■
Sleep mode operation
■
Full-featured real time clock (RTC)
❐
Watchdog timer
❐
Clock alarm with programmable interrupts
❐
Backup power fail indication
❐
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
❐
Capacitor or battery backup for RTC
❐
Backup current of 0.45
A
(typical)
■
Low power consumption
❐
Active current of 75 mA at 45 ns
❐
Standby mode current of 750
A
❐
Sleep mode current of 10
A
■
■
■
■
Functional Description
The Cypress CY14B116K/CY14B116M combines a 16-Mbit
nvSRAM with a full-featured RTC in a monolithic integrated
circuit. The nvSRAM is a fast SRAM with a nonvolatile element
in each memory cell. The memory is organized as 2048 K bytes
of 8 bits each or 1024 K words of 16 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data residing in the nonvolatile elements do not
change when data is written to the SRAM. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL operations
are also available under software control.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high-accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer.
For a complete list of related documentation, click
here.
Operating voltage: V
CC
= 2.7 V to 3.6 V
Industrial temperature: –40
C
to +85
C
Packages
❐
44-pin thin small-outline package (TSOP II)
❐
54-pin thin small-outline package (TSOP II)
❐
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
■
Cypress Semiconductor Corporation
Document #: 001-67786 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 7, 2015
CY14B116K/CY14B116M
Logic Block Diagram
[1, 2, 3]
V CC V CAP V RTCcap V RTCbat
POWER CONTROL
SLEEP MODE
CONTROL
STORE / RECALL
CONTROL
HSB
ZZ
QUANTUMTRAP
4096 X 4096
STORE
ROW DECODER
RECALL
STATIC RAM
ARRAY
4096 X 4096
SOFTWARE
DETECT
A 2-A14
A 0-A11
OE
[4]
CE
WE
CONTROL LOGIC
BLE
BHE
OUTPUT BUFFERS
INPUT BUFFERS
SENSE AMPS
ZZ
X out
X in
INT
DQ 0-DQ 15
COLUMN IO
RTC
COLUMN DECODER
MUX
A 0-A20
A 12-A20
Notes
1. Address A
0
–A
20
for ×8 configuration and address A
0
–A
19
for ×16 configuration.
2. Data DQ
0
–DQ
7
for ×8 configuration and data DQ
0
–DQ
15
for ×16 configuration.
3. BLE, BHE are applicable for x16 configuration.
4. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE
1
and CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
Document #: 001-67786 Rev. *J
Page 2 of 42
CY14B116K/CY14B116M
Contents
Pinouts .............................................................................. 4
Device Operation .............................................................. 6
SRAM Read ....................................................................... 6
SRAM Write ....................................................................... 6
AutoStore Operation (Power-Down) ............................... 6
Hardware STORE (HSB) Operation................................. 7
Hardware RECALL (Power-Up) ....................................... 7
Software STORE ............................................................... 7
Software RECALL............................................................. 7
Sleep Mode........................................................................ 8
Preventing AutoStore....................................................... 9
Data Protection ............................................................... 10
Real Time Clock Operation............................................ 10
nvTime Operation...................................................... 10
Clock Operations....................................................... 10
Reading the Clock ..................................................... 10
Setting the Clock ....................................................... 10
Backup Power ........................................................... 10
Stopping and Starting the Oscillator.......................... 11
Calibrating the Clock ................................................. 11
Alarm ......................................................................... 11
Watchdog Timer ........................................................ 12
Programmable Square Wave Generator................... 12
Power Monitor ........................................................... 12
Backup Power Monitor .............................................. 13
Interrupts ................................................................... 13
Flags Register ........................................................... 14
RTC External Components ....................................... 15
PCB Design Considerations for RTC............................ 15
Layout Requirements ................................................ 15
Maximum Ratings........................................................... 22
Operating Range............................................................. 22
DC Electrical Characteristics ........................................ 22
Data Retention and Endurance ..................................... 23
Capacitance ....................................................................
Thermal Resistance........................................................
AC Test Conditions ........................................................
RTC Characteristics .......................................................
AC Switching Characteristics .......................................
AutoStore/Power-Up RECALL Characteristics............
Sleep Mode Characteristics...........................................
Software Controlled STORE and RECALL
Characteristics................................................................
Hardware STORE Characteristics.................................
For ×16 Configuration ...............................................
Truth Table For SRAM Operations................................
For ×8 Configuration .................................................
For ×16 Configuration ...............................................
Ordering Information......................................................
Package Diagrams..........................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Errata ...............................................................................
Part Numbers Affected ..............................................
16-Mbit (2048 K × 8, 1024 K × 16) nvSRAM
Qualification Status ...................................................
16-Mbit (2048 K × 8, 1024 K × 16) nvSRAM
Errata Summary ........................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
23
23
24
24
25
29
30
31
32
33
33
33
34
35
36
39
39
39
40
40
40
40
42
44
44
44
44
44
44
Document #: 001-67786 Rev. *J
Page 3 of 42
CY14B116K/CY14B116M
Pinouts
Figure 1. Pin Diagram: 44-Pin TSOP II (
×
8)
Figure 2. Pin Diagram: 54-Pin TSOP II (
×
16)
INT
A
19
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
INT
A
20
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44 - TSOP II
(x8)
Top View
(not to scale)
HSB
NC
[5]
A
19
A
18
A
17
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
HSB
A
18
A
17
A
16
54 - TSOP II
(x16)
Top View
(not to scale)
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
Xout
Xin
V
RTCcap
V
RTCbat
Figure 3. Pin Diagram: 165-Ball FBGA (×16)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
ZZ
NC
NC
NC
HSB
NC
NC
NC
NC
NC
INT
NC
NC
2
A
6
DQ
0
NC
DQ
2
V
CAP
DQ
3
NC
NC
NC
NC
DQ
5
NC
DQ
6
NC
NC
3
A
8
DQ
1
NC
NC
NC
NC
NC
V
CC
NC
DQ
4
NC
NC
DQ
7
NC
A
15
4
WE
A
4
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
A
13
NC
5
BLE
BHE
A
0
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
A
11
A
19
A
17
6
CE
1
CE
2
A
7
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
10
V
RTCbat
V
RTCcap
7
NC
NC
A
1
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
A
9
A
18
A
16
8
OE
A
2
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
A
12
NC
[5]
9
A
5
NC
NC
X
in
X
out
NC
NC
V
CC
NC
NC
NC
NC
NC
NC
A
14
10
A
3
NC
DQ
15
NC
DQ
13
NC
NC
NC
DQ
8
NC
NC
DQ
10
NC
DQ
11
NC
11
NC
NC
DQ
14
NC
NC
DQ
12
NC
NC
NC
NC
DQ
9
NC
NC
NC
NC
Note
5. Address expansion for the 32-Mbit. NC pin not connected to die.
Document #: 001-67786 Rev. *J
Page 4 of 42
CY14B116K/CY14B116M
Table 1. Pin Definitions
Pin Name
A
0
–A
20
A
0
–A
19
DQ
0
–DQ
7
Input/Output
DQ
0
–DQ
15
WE
CE
Input
CE
1,
CE
2
OE
BLE
BHE
ZZ
[6]
I/O Type
Input
Description
Address inputs. Used to select one of the 2,097,152 bytes of the nvSRAM for the ×8 configuration.
Address inputs. Used to select one of the 1,048,576 words of the nvSRAM for the ×16 configuration.
Bidirectional data I/O lines for the ×8 configuration.
Used as input or output lines depending on
operation.
Bidirectional data I/O lines for the ×16 configuration.
Used as input or output lines depending on
operation.
Write Enable input, Active LOW.
When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable input in TSOP II package, Active LOW.
When LOW, selects the chip. When HIGH,
deselects the chip.
Chip Enable input in FBGA package.
The device is selected and a memory access begins on the
falling edge of CE
1
(while CE
2
is HIGH) or the rising edge of CE
2
(while CE
1
is LOW).
Output Enable, Active LOW.
The Active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Byte Enable, Active LOW.
When selected LOW, enables DQ
7
–DQ
0
.
Byte Enable, Active LOW.
When selected LOW, enables DQ
15
–DQ
8
.
Sleep Mode Enable.
When the ZZ pin is pulled LOW, the device enters a low-power Sleep mode and
consumes the lowest power. Since this input is logically AND’ed with CE, ZZ must be HIGH for normal
operation.
Crystal connection.
Drives crystal on start-up.
Crystal connection.
For 32.768-KHz crystal.
Input
Input
Input
Input
Input
Output
Input
X
out[7]
X
in[7]
V
RTCcap[7]
Power Supply
Capacitor supplied backup RTC supply voltage.
Left unconnected if V
RTCbat
is used.
V
RTCbat[7]
INT
[7]
Power Supply
Battery supplied backup RTC supply voltage.
Left unconnected if V
RTCcap
is used.
Output
Interrupt output/calibration/square wave.
Programmable to respond to the clock alarm, the watchdog
timer, and the power monitor. In addition, programmable to be either Active HIGH (push or pull) or LOW
(open drain). In the Calibration mode, a 512-Hz square wave is driven out. In the Square Wave mode,
you can select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a continuous output.
V
CC
V
SS
HSB
Power Supply
Power supply inputs to the device.
Power Supply
Ground for the device.
Must be connected to ground of the system.
Hardware STORE Busy (HSB).When
LOW, this output indicates that a Hardware STORE is in
progress. When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. After each
Input/Output Hardware and Software STORE operation, HSB is driven HIGH for a short time (t
HHHD
) with standard
output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
Power Supply
NC
AutoStore capacitor.
Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect.
Die pads are not connected to the package pin.
V
CAP
NC
Notes
6. Sleep mode feature is offered only in the 165-ball FBGA package.
7. Left unconnected if RTC feature is not used.
Document #: 001-67786 Rev. *J
Page 5 of 42
