CY22393
Automotive Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Automotive Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Features
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CyClocksRT™ software support
AEC-Q100 Qualified
Available in A and E grade
Three integrated phase-locked loops (PLLs)
Ultra-wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
Improved linear crystal load capacitors
Flash programmability with external programmer
Field-programmable
Low-jitter, high-accuracy outputs
Power management options (Shutdown, OE, Suspend)
Configurable crystal drive strength
Frequency select through three external LVTTL inputs
3.3-V operation
16-pin TSSOP package
Advanced Features
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Two-wire serial interface for in-system configurability
Configurable output buffer
Digital VCXO
Functional Description
The CY22393 has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
Logic Block Diagram – CY22393
XTALIN
XTALOUT
OSC.
XBUF
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
PLL2
11-Bit P
8-Bit Q
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
CLKB
4x4
Crosspoint
Switch
Divider
/2, /3, or /4
CLKE
SHUTDOWN/OE
SCLK
SDAT
S2/SUSPEND
Divider
7-Bit
CLKD
Divider
7-Bit
CLKC
Divider
7-Bit
CLKA
Cypress Semiconductor Corporation
Document Number: 001-73555 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 23, 2014
CY22393
Contents
lPin
Configuration.............................................................
Configurable PLLs.......................................................
General-Purpose Inputs ..............................................
Crystal Input ................................................................
Crystal Drive Level and Power ....................................
Digital VCXO ...............................................................
Output Configuration ...................................................
Power-Saving Features...............................................
Improving Jitter............................................................
Power Supply Sequencing ..........................................
CyClocksRT Software ......................................................
Device Programming........................................................
Junction Temperature Limitations ...............................
Dynamic Updates ........................................................
Memory Bitmap Definitions .............................................
Clk{A–D}_Div[6:0]........................................................
ClkE_Div[1:0]...............................................................
Clk*_FS[2:0] ................................................................
Xbuf_OE......................................................................
PdnEn..........................................................................
Clk*_ACAdj[1:0]...........................................................
Clk*_DCAdj[1:0] ..........................................................
PLL*_Q[7:0].................................................................
PLL*_P[9:0] .................................................................
PLL*_P0 ......................................................................
PLL*_LF[2:0] ...............................................................
PLL*_En ......................................................................
DivSel ..........................................................................
OscCap[5:0] ................................................................
OscDrv[1:0] .................................................................
Reserved .....................................................................
Serial Programming Bitmaps – Summary Tables .........
Serial Bus Programming Protocol and Timing..............
Default Startup Condition for the CY22393 .................
Device Address ...........................................................
3
3
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
7
8
8
8
Data Valid.................................................................... 8
Data Frame ................................................................. 8
Acknowledge Pulse ..................................................... 8
Write Operations............................................................... 8
Writing Individual Bytes ............................................... 8
Writing Multiple Bytes.................................................. 8
Read Operations............................................................... 8
Current Address Read................................................. 8
Random Read ............................................................. 8
Sequential Read.......................................................... 8
Serial Programming Interface Timing........................... 10
Serial Programming Interface Timing Specifications . 10
Electrical Specifications ................................................ 11
Absolute Maximum Conditions.................................. 11
Operating Conditions................................................. 11
Recommended Crystal Specifications....................... 11
3.3 V Electrical Characteristics.................................. 11
3.3 V Switching Characteristics................................. 12
Switching Waveforms .................................................... 13
Test Circuit...................................................................... 14
Ordering Information...................................................... 15
Possible Configurations............................................. 15
Package Diagram............................................................ 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Document Number: 001-73555 Rev. *B
Page 2 of 19
CY22393
Pin Configuration
Figure 1. Pin Diagram - 16-Pin TSSOP CY22393
Pin Definitions
Name
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
CLKB
CLKA
GND
SDAT (S0)
SCLK (S1)
AV
DD
S2/
SUSPEND
SHUTDOWN/
OE
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Configurable clock output C
Power supply
Analog ground
Reference crystal input or external reference clock input
Reference crystal feedback
Buffered reference clock output
Configurable clock output D
Configurable clock output E
Configurable clock output B
Configurable clock output A
Ground
Serial port data. S0 value latched during start-up
Serial port clock. S1 value latched during start-up
Analog power supply
General-purpose input for frequency control; bit 2. Optionally, Suspend mode control input
Places outputs in tristate condition and shuts down chip when LOW. Optionally, only places outputs
in tristate condition and does not shut down chip when LOW
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
cross point switch. The frequency of PLL2 is changed using
serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross point switch. The frequency of PLL3 is changed using
serial programming.
Description
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
cross point switch. The output of PLL1 is also sent to a /2, /3, or
/4 synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming or
by external CMOS inputs, S0, S1, and S2. See
General-Purpose
Inputs on page 4
for more detail.
Document Number: 001-73555 Rev. *B
Page 3 of 19
CY22393
General-Purpose Inputs
S2 is a general-purpose input that is programmed to enable two
frequency settings. The options that switch with this
general-purpose input are as follows: the frequency of PLL1, the
output divider of CLKB, and the output divider of CLKA.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indices into
this array.
CLKA and CLKB have seven-bit dividers that point to one of the
two programmable settings (register 0 or register 1). Both clocks
share a single register control and both must be set to register 0,
or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0, 0, 0 to 1, 1, 1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be
glitch-free.
Digital VCXO
The serial programming interface is used to dynamically change
the capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency.
For special pullable crystals specified by Cypress, the
capacitance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects all
frequencies on all PLLs in a similar manner because all
frequencies are derived from the single reference.
Output Configuration
Under normal operation there are four internal frequency
sources that are routed through a programmable cross point
switch to any of the four programmable 7-bit output dividers. The
four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
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Crystal Input
The input crystal oscillator is an important feature of CY24293
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
enables maximum compatibility with crystals from various
manufacturers. Parallel resonant, fundamental mode crystals
should be used.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375 pF for a total crystal load range of 6 pF to
30 pF. Typical crystals have a C
L
specification in the range of
12 pF to 18 pF.
For driven clock inputs, the input load capacitors can be
bypassed. This allows the clock chip to accept driven frequency
inputs up to 166 MHz. If the application requires a driven input,
leave XTALOUT floating.
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CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section
General-Purpose Inputs
for more
information.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section
General-Purpose Inputs
for more
information.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
XBUF is the buffered reference.
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The clock outputs are designed to drive a single-point load with
a total lumped load capacitance of 15 pF. While driving multiple
loads is possible with the proper termination, it is generally not
recommended.
Power-Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the V
DD
pins is less
than 5 mA (typical). Relock the PLLs after leaving the shutdown
mode.
The S2/SUSPEND input is configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs are shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tristate condition.
Crystal Drive Level and Power
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. For a specific
voltage swing, power dissipation in the crystal is proportional to
ESR and proportional to the square of the crystal frequency.
(Note that the actual ESR is sometimes much less than the value
specified by the crystal manufacturer.) Power is also almost
proportional to the square of C
L
.
Power can be reduced to less than the DL specified in
Recom-
mended Crystal Specifications on page 11
by selecting a
reduced frequency crystal with low C
L
and low R
1
(ESR).
Document Number: 001-73555 Rev. *B
Page 4 of 19
CY22393
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
Dynamic Updates
The output divider registers are not synchronized with the output
clocks. Changing the divider value of an active output is likely
cause a glitch on that output.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL can cause the PLL to try to lock
an out-of-bounds condition. Therefore, you must turn off the PLL
being programmed during the update. Do this by setting the
PLL*_En bit LOW.
PLL1, CLKA, and CLKB each have multiple registers supplying
data. To program these resources safely, always program an
inactive register, and then transition to that register. This allows
these resources to stay active during programming.
The serial interface is active even with the SHUTDOWN/OE pin
LOW as the serial interface logic uses static components and is
completely self-timed. The part does not meet the I
DDS
current
limit with transitioning inputs.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning and
allows superior jitter performance.
Power Supply Sequencing
There are no power supply sequencing requirements. The part
is not fully operational until all V
DD
pins are brought up to the
voltages specified in the
Operating Conditions on page 11.
All grounds must be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation software application that
allows users to configure this device. The easy-to-use interface
offers complete control of the many features of this device
including, but not limited to, input frequency, PLL and output
frequencies, and different functional options. It checks the data
sheet frequency range limitations and automatically applies
performance tuning. CyClocksRT also has a power estimation
feature that allows you to see the power consumption of a
specific configuration. You can download a free copy of
CyberClocks that includes CyClocksRT on Cypress’s web site,
www.cypress.com.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency rules
that are not documented in this datasheet, but are required for
proper operation of the device. Check these rules by using the
latest version of CyClocksRT.
Memory Bitmap Definitions
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting between 1 and 127
may be used by programming the value of the desired divider
into this register. Odd divide values are automatically duty-cycle
corrected. Setting a divide value of zero powers down the divider
and forces the output to a tristate condition.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which, in turn, is selected by S2, S1, and S0). This
allows the output divider value to change dynamically.
ClkE_Div[1:0]
CLKE has a simpler divider (see
Table 1).
Table 1. ClkE Divider
ClkE_Div[1:0]
00
01
10
11
Off
PLL1 0
°
Phase/4
PLL1 0
°
Phase/2
PLL1 0
°
Phase/3
ClkE Output
Device Programming
Part numbers starting with CY22392F are ‘field programmable’
devices. Field programmable devices are shipped
unprogrammed and must be programmed prior to installation on
a PCB. After a programming file (.jed) is created using the
CyberClocks software, devices can be programmed in small
quantities using the CY3672 programmer and CY3698
[1]
adapter. Programming of the clock device should be done at
temperatures < 75
°C.
Volume programming is available through
Cypress Semiconductor’s value-added distribution partners or
by using third-party programmers from BP Microsystems, HiLo
Systems, and others. For sufficiently large volumes, Cypress can
supply pre-programmed devices with a part number extension
that is configuration-specific.
Clk*_FS[2:0]
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1, PLL2,
and PLL3. Each PLL provides both positive and negative phased
outputs, for a total of seven clock sources (see
Table 2).
Note
that the phase is a relative measure of the PLL output phases.
No absolute phase relation exists at the outputs.
Junction Temperature Limitations
It is possible to program this family such that the maximum
junction temperature rating is exceeded. The package
θ
JA
is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the junction
temperature and package power dissipation maximum ratings.
Note
1. CY3698 only supports programming of only the 16-pin TSSOP package.
Document Number: 001-73555 Rev. *B
Page 5 of 19
