Highest performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Application compatibility for a wide variety of designs
Table 1. Frequency Table
Part Number
Outputs
Input Frequency Range
Output Frequencies
VCXO Control
Curve
Other Features
CY241V8A-11
1
13.5 MHz pullable crystal input One copy of 54 MHz
per Cypress specification
linear
Pinout-compatible with CY2411
Block Diagram
13.5 XIN
OSC
XOUT
PLL
Output
Divider
54 MHz
VCXO
VDD
VSS
Pin Configuration
Figure 1. CY241V8A-11 8-pin SOIC
Pin Descriptions
Name
Pin Number
Description
XIN
VDD
VCXO
VSS
54 MHz
XOUT
1
2, 5
3
4, 7
6
8
Reference crystal input
Voltage supply
Input analog control for VCXO
Ground
54 MHz clock output
Reference crystal output
Junction temperature ............................... –40
C
to +125
C
Data retention at Tj = 125
C
................................ > 10 years
Package power dissipation ....................................... 350 mW
ESD (human body model) MIL-STD-883................. > 2000 V
Absolute Maximum Conditions
Supply voltage (V
DD
) .......................................–0.5 to +7.0 V
DC input voltage ..................................... –0.5 V to V
DD
+ 0.5
Storage temperature (Non-condensing) ... –55
C
to +125
C
Cypress Semiconductor Corporation
Document #: 38-07654 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 9, 2010
[+] Feedback
CY241V8A-11
Pullable Crystal Specifications
[1]
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
Parameter
VDD
T
A
C
LOAD
t
PU
Operating voltage
Ambient temperature
Max load capacitance
Power-up time for all V
DD
pins to reach minimum specified voltage (power
ramps must be monotonic)
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Fundamental mode
Ratio of third overtone mode ESR to Ratio used because typical R
1
values
fundamental mode ESR
are much less than the maximum spec
Crystal drive level
Third overtone separation from 3 ×
F
NOM
Third overtone separation from 3 ×
F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capaci-
tance
Crystal motional capacitance
Description
No external series resistor assumed
High side
Low side
Comments
Parallel resonance, fundamental mode,
AT cut
Min
–
–
–
3
150
300
–
–
180
14.4
Min
3.135
0
–
0.05
Typ
13.5
14
–
–
–
–
–
–
–
18
Typ
3.3
–
–
–
Max
–
–
25
–
–
–
–150
7
250
21.6
Max
3.465
70
15
500
Unit
MHz
pF
–
W
ppm
ppm
pF
–
fF
Unit
V
C
pF
ms
Recommended Operating Conditions
DC Electrical Specifications
Parameter
I
OH
I
OL
C
IN
V
VCXO
f
XO
[2]
I
VDD
Parameter
[3]
DC
ER
EF
t
9
t
10
Name
Output HIGH current
Output LOW current
Input capacitance
VCXO input range
VCXO pullability range
Supply current
Name
Output duty cycle
Rising edge rate
Falling edge rate
Clock jitter
PLL lock time
Description
Duty cycle is defined in
Figure 2 on page 3,
50% of V
DD
Output clock edge rate, measured from
20% to 80% of V
DD
, C
LOAD
= 15 pF.
see
Figure 3 on page 3.
Output clock edge rate, measured from
80% to 20% of V
DD
, C
LOAD
= 15 pF.
see
Figure 3 on page 3.
Peak-to-peak period jitter
Low side
High side
Description
V
OH
= V
DD
– 0.5 V, V
DD
= 3.3 V
V
OL
= 0.5 V, V
DD
= 3.3 V
Except XIN, XOUT pins
Min
12
12
–
0
–
115
–
Min
45
0.8
0.8
–
–
Typ
24
24
–
–
–
–
30
Typ
50
1.4
1.4
–
–
Max
–
–
7
V
DD
–115
–
35
Max
55
–
–
100
3
Unit
mA
mA
pF
V
ppm
ppm
mA
Unit
%
V / ns
V / ns
ps
ms
AC Electrical Specifications
(V
DD
= 3.3 V)
[3]
Notes
1. Crystals that meet this specification include: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board
PCB设计
