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CY24713KSXC

IC clock gen set-top 8-soic

器件类别:半导体    模拟混合信号IC   

厂商名称:Cypress(赛普拉斯)

器件标准:  

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CY24713
Set-top Box Clock Generator with VCXO
Features
Benefits
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
VCXO with analog adjust
3.3V Operation
8-pin SOIC
High-performance PLL tailored for Set Top Box applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Meet industry standard voltage platforms
Industry standard packaging saves on board space
Part Number
CY24713
Outputs
3
Input Frequency Range
27-MHz pullable crystal input
per Cypress specification
Output Frequencies
4.9152 MHz, 13.5 MHz, 27 MHz
Logic Block Diagram
Pin Configuration
Figure 1. CY24713, 8-Pin SOIC
Table 1. Pin Definition
Name
XIN
VDD
VCXO
VSS
CLK_B
CLK_A
CLK_C
XOUT
[1]
1
2
3
4
5
6
7
8
Number
Description
Reference Crystal Input
3.3V Voltage Supply
Input Analog Control for VCXO
Ground
13.5-MHz Clock Output
4.9152-MHz Clock Output
27-MHz Clock Output
Reference Crystal Output
Note
1. Float X
OUT
if X
IN
is externally driven.
Cypress Semiconductor Corporation
Document #: 38-07396 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 26, 2010
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CY24713
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Supply Voltage
Storage Temperature
[2]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electrostatic Discharge
Analog Input
Description
Min
–0.5
–65
V
SS
– 0.3
V
SS
– 0.3
–0.5
Max
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
2000
7.0
Unit
V
°C
°C
V
V
V
V
Pullable Crystal Specifications
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
Description
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Fundamental mode
Ratio of third overtone mode ESR to fundamen- Ratio used because typical R
1
tal mode ESR
values are much less than the
maximum spec.
Crystal drive level
Third overtone separation from 3*F
NOM
Third overtone separation from 3*F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
No external series resistor as-
sumed
High side
Low side
Condition
Parallel resonance, funda-
mental mode, AT cut
Min
3
Typ.
27
14
Max
25
Unit
MHz
pF
Ω
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
300
180
14.4
0.5
18
2.0
–150
7
250
21.6
mW
ppm
ppm
pF
pF
Recommended Operating Conditions
Parameter
V
DD
T
A
C
LOAD
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
Description
Min
3.135
0
0.05
Typ.
3.3
Max
3.465
70
15
500
Unit
V
°C
pF
ms
DC Electrical Characteristics
Parameter
I
OH
I
OL
C
IN
I
IZ
f
ΔXO
V
VCXO
I
VDD
Description
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
VCXO pullability range
VCXO input range
Supply Current
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
Min
12
12
±150
0
Typ.
24
24
5
25
Max
7
V
DD
30
Unit
mA
mA
pF
μA
ppm
V
mA
Note
2. Rated for 10 years
Document #: 38-07396 Rev. *B
Page 2 of 5
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CY24713
AC Electrical Characteristics
(V
DD
= 3.3V)
Parameter
[3]
DC
ER
0
EF
1
t
9
t
10
Description
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Clock Jitter
PLL Lock Time
Figure 2. Test Circuit
V DD
0.1
μF
OUTPUTS
Conditions
Duty Cycle is defined in
Figure 3
50% of V
DD
Output Clock Edge Rate, Measured from 20% to
80% of V
DD,
C
LOAD
= 15 pF
Figure 4.
Output Clock Edge Rate, Measured from 80% to
20% of V
DD,
C
LOAD
= 15 pF
Figure 4.
Peak-Peak period jitter maximum absolute jitter
Min
45
0.8
0.8
Typ.
50
1.4
1.4
200
Max
55
250
3
Unit
%
V/ns
V/ns
ps
ms
CLK out
C LOAD
GND
Figure 3. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Figure 4. Rise and Fall Time Definitions: ER = 0.6 x V
DD
/t3, EF = 0.6 x V
DD
/t4
t3
80%
t4
CLK
20%
Note
3. Not 100% tested
Document #: 38-07396 Rev. *B
Page 3 of 5
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CY24713
Ordering Information
Ordering Code
Pb-free
CY24713KSXC
CY24713KSXCT
8-pin SOIC
8-pin SOIC-Tape and Reel
Commercial
Commercial
3.3V
3.3V
Package Type
Operating Range
Operating Voltage
Package Diagram
Figure 5. 8-Pin (150-Mil) SOIC S8
51-85066 *D
Document #: 38-07396 Rev. *B
Page 4 of 5
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CY24713
Document History Page
Document Title: CY24713 Set-top Box Clock Generator with VCXO
Document Number: 38-07396
Rev.
**
*A
ECN No.
333175
2440886
Orig. of
Change
RGL
AESA
Submission
Date
See ECN
See ECN
New Data Sheet
Updated template. Added Note “Not recommended for new designs.”
Added part number CY24713KSXC, and CY24713KSXCT in ordering infor-
mation table.
Replaced Lead-Free with Pb-Free.
Removed inactive parts from ordering information table
Updated package diagram
Description of Change
*B
2899683
CXQ
03/26/10
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at
Cypress Locations.
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© Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07396 Rev. *B
Revised March 26, 2010
Page 5 of 5
All products and company names mentioned in this document may be the trademarks of their respective holders.
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参数对比
与CY24713KSXC相近的元器件有:CY24713KSXCT。描述及对比如下:
型号 CY24713KSXC CY24713KSXCT
描述 IC clock gen set-top 8-soic IC clock gen set-top 8-soic
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