CY2544
CY2546
CY2548
Quad PLL Programmable Clock Generator
with Spread Spectrum
Quad PLL Programmable Clock Generator with Spread Spectrum
Features
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Ability to synthesize nonstandard frequencies with Fractional-N
capability
Up to nine clock outputs with programmable drive strength
Glitch free outputs while frequency switching
24-pin QFN package
Commercial and Industrial temperature ranges
Four fully integrated phase locked loops (PLLs)
Input frequency range
❐
External crystal: 8 to 48 MHz for CY2544 and CY2546
❐
External reference: 8 to 166 MHz clock
Reference clock input voltage range
❐
2.5 V, 3.0 V, and 3.3 V for CY2548
❐
1.8 V for CY2544 and CY2546
Wide operating output frequency range
❐
3 to 166 MHz
Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
VDD supply voltage options:
❐
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
❐
1.8 V for CY2546
Selectable output clock voltages:
❐
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
❐
1.8 V for CY2546
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Power down, output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
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Benefits
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Multiple high performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using spread
spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of Zero PPM frequency synthesis error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low power systems
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Logic Block Diagram
CLKIN
Crossbar
Switch
OSC
PLL1
Output
Dividers
and
Bank
2
CLK1
Bank
1
XIN/
EXCLKIN
XOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL2
Drive
Strength
Control
Bank
PLL3
(SS)
3
CLK8
CLK9
PLL4
(SS)
SSON
PD#/OE
Cypress Semiconductor Corporation
Document Number: 001-12563 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 8, 2014
CY2544
CY2546
CY2548
Contents
Device Selection Guide .................................................... 3
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Pinout ................................................................................ 4
Pin Definitions .................................................................. 5
General Description ......................................................... 5
Four Configurable PLLs .............................................. 5
Input Reference Clocks ............................................... 5
Multiple Power Supplies .............................................. 5
Output Bank Settings .................................................. 6
Output Source Selection ............................................. 6
Spread Spectrum Control ............................................ 6
Frequency Select ........................................................ 6
Glitch-Free Frequency Switch ..................................... 6
PD#/OE Mode ............................................................. 6
Output Drive Strength .................................................. 6
Generic Configuration and Custom Frequency ........... 6
Absolute Maximum Conditions ....................................... 7
Recommended Operating Conditions ............................ 7
DC Electrical Specifications ............................................ 7
AC Electrical Specifications ............................................ 9
Configuration Example for C-C Jitter ............................. 9
Recommended Crystal Specification ............................. 9
Recommended Crystal Specification ........................... 10
Test and Measurement Setup ........................................ 10
Voltage and Timing Definitions ..................................... 10
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definitions ......................................... 12
Package Drawing and Dimensions ............................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-12563 Rev. *H
Page 2 of 17
CY2544
CY2546
CY2548
Device Selection Guide
Device
CY2544
CY2546
CY2548
Crystal Input
Yes
Yes
No
EXCKLKIN Input
1.8 V LVCMOS
1.8 V LVCMOS
CLKIN Input
VDD
VDD_CLK_BX
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
1.8 V LVCMOS
1.8 V
1.8 V
2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V 2.5 V, 3.0 V, 3.3 V
Pinout
Figure 1. 24-pin QFN pinout
CY2544 / CY2548
XIN/
EXCLKIN
EXCLKIN
CLKIN
CLKIN
XOUT
CLK9
20
CLK9
24
23
22
21
20
19
24
23
22
21
GND
CLK1
VDD_CLK_B1
PD#OE
NC
CLK2
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
GND
19
GND
DNU
VDD
VDD
GND
CLK1
VDD_CLK_B1
PD#OE
NC
CLK2
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
2
17
2
17
3
CY2544
24LD QFN
16
3
CY2548
24LD QFN
16
4
15
4
15
5
14
5
14
6
13
6
13
7
8
9
10
11
12
7
8
9
10
11
12
GND
OE/FS1
CLK3/FS0
CLK4/FS2
CLK3/FS0
OE/FS1
CLK4/FS2
CLK5
Pin Definitions
CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
1
2
3
4
5
6
7
8
9
10
Name
GND
CLK1
VDD_CLK_B1
PD#/OE
NC
CLK2
GND
CLK3/FS0
OE/FS1
CLK4/FS2
I/O
Power
Output
Power
Input
NC
Output
Power
Power supply ground
Programmable clock output.
Output voltage depends on
VDD_CLK_B1
voltage
Power supply for bank1, (CLK1, CLK2, CLK3) Outputs:
2.5 V/3.0 V/3.3 V
Description
Multifunction programmable pin.
Output enable or power-down mode
No Connect
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B1
voltage
Power supply ground
Output/input
Multifunction programmable pin.
Programmable clock
output clock or frequency
select pin. Output voltage of
CLK3
depends on
VDD_CLK_B1
voltage
Input
Multifunction programmable pin.
Output enable or frequency select pin
Output/input
Multifunction programmable pin.
Programmable clock output or frequency select
input pin.
Output voltage of
CLK4
depends on
VDD_CLK_B2
voltage
Document Number: 001-12563 Rev. *H
CLK5
GND
GND
GND
Page 3 of 17
CY2544
CY2546
CY2548
Pin Definitions
(continued)
CY2544/CY2548 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
CLK5
GND
CLK6
VDD_CLK_B2
CLK7/SSON
VDD_CLK_B3
CLK8
GND
GND
CLK9
CLKIN
VDD
XOUT
DNU
XIN/EXCLKIN
EXCLKIN
I/O
Output
Power
Output
Power
Power supply ground
Programmable clock
output.
Output voltage depends on
VDD_CLK_B2
voltage
Power supply for bank2, (CLK4, CLK5, CLK6) Outputs.
2.5 V/3.0 V/3.3 V
Description
Programmable clock output.
Output voltage depends on
VDD_CLK_B2
voltage
Output/input
Multifunction programmable pin.
Programmable clock output or
spread spectrum
ON/OFF control input pin. Output voltage of
CLK7
depends on Bank3 voltage
Power
Output
Power
Power
Output
Input
Power
Output
Output
Input
Input
Power supply for bank3, (CLK7, CLK8, CLK9) Outputs.
2.5 V/3.0 V/3.3 V
Programmable output clock.
Output voltage depends on Bank3 voltage
Power supply ground
Power supply ground
Programmable clock
output.
Output voltage depends on
VDD_CLK_B3
voltage
2.5 V/3.0 V/3.3 V
reference clock input.
The signal level of CLKIN input must
track
VDD power supply on pin 22.
Power supply.
2.5 V/3.0 V/3.3 V
Crystal output
for CY2544
Do not use this pin
for CY2548
Crystal input or 1.8 V external clock input for CY2544
2.5 V/3.0 V/3.3 V
external clock input for CY2548
Pinout
Figure 2. 24-pin QFN pinout
CY2546
XIN/
EXCLKIN
CLKIN
XOUT
CLK9
20
VDD
24
23
22
21
GND
19
GND
CLK1
VDD_CLK_B1
PD#OE
VDD
CLK2
1
18
GND
CLK8
VDD_CLK_B3
CLK7/SSON
VDD_CLK_B2
CLK6
2
17
3
CY2546
24LD QFN
16
4
15
5
14
6
13
7
8
9
10
11
12
OE/FS1
Document Number: 001-12563 Rev. *H
CLK3/FS0
CLK4/FS2
CLK5
GND
GND
Page 4 of 17
CY2544
CY2546
CY2548
Pin Definitions
CY2546 (VDD = 1.8 V Supply)
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
GND
CLK1
VDD_CLK_B1
PD#/OE
VDD
CLK2
GND
CLK3/FS0
OE/FS1
CLK4/FS2
CLK5
GND
CLK6
VDD_CLK_B2
CLK7/SSON
I/O
Power
Output
Power
Input
Power
Output
Power
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B1 voltage
Power supply for bank1, (CLK1, CLK2, CLK3) Outputs.
1.8 V
Description
Multifunction programmable pin.
Output enable or power down mode
Power supply.
1.8 V
Programmable clock
output.
Output voltage depends on VDD_CLK_B1 voltage
Power supply ground
Output/Input
Multifunction programmable pin.
Programmable clock
output or frequency select
input pin. Output voltage of
CLK3
depends on VDD_CLK_B1 voltage
Input
Multifunction programmable pin.
Output enable or frequency select pin
Output/Input
Multifunction programmable pin.
Programmable clock output or frequency select
input pin.
Output voltage of
CLK4
depends on VDD_CLK_B2 voltage
Output
Power
Output
Power
Programmable clock
output.
Output voltage depends on VDD_CLK_B2 voltage
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B2 voltage
Power supply for bank2, (CLK4, CLK5, CLK6) Outputs.
1.8 V
Output/input
Multifunction programmable pin.
Programmable clock output or
spread spectrum
ON/OFF control input pin. Output voltage of
CLK7
depends on VDD_CLK_B3
voltage
Power
Output
Power
Power
Output
Input
Power
Output
Input
Power supply for bank3, (CLK7, CLK8, CLK9) Outputs.
1.8 V
Programmable clock
output.
Output voltage depends on VDD_CLK_B3 voltage
16
17
18
19
20
21
22
23
24
VDD_CLK_B3
CLK8
GND
GND
CLK9
CLKIN
VDD
XOUT
XIN/EXCLKIN
Power supply ground
Power supply ground
Programmable clock
output.
Output voltage depends on VDD_CLK_B3 voltage
External 1.8 V low voltage reference clock input
Power supply.
1.8 V
Crystal output
Crystal input or 1.8 V external clock input
for CY2544 and CY2546 is 1.8 V. This gives user an option for
this device to be compatible for different input clock voltage
levels in the system.
There is provision for a secondary reference clock input, CLKIN
with applied frequency range of 8 MHz to 166 MHz. When CLKIN
signal at pin 21 is used as a reference input to the PLL, a valid
signal at EXCLKIN (as specified in the AC and DC Electrical
Specification table) must be present for the devices to operate
properly.
General Description
Four Configurable PLLs
The CY2544, CY2548 and CY2546 have four programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having four PLLs is that a
single device generates up to four independent frequencies from
a single crystal.
Input Reference Clocks
The input to the CY2544, CY2548 and CY2546 can be either a
crystal or a clock signal. The input frequency range for crystal
(XIN) is 8 MHz to 48 MHz and that for external reference clock
(EXCLKIN) is 8 MHz to 166 MHz. The voltage range for the
reference clock input of CY2548 is 2.5 V/3.0 V/3.3 V while that
Document Number: 001-12563 Rev. *H
Multiple Power Supplies
These devices are designed to operate at internal supply voltage
of 1.8 V. In the case of the high voltage part (CY2544/CY2548),
an internal regulator is used to generate 1.8 V from the
2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low
Page 5 of 17
