CY25C01/02/04/08/16
1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8)
SPI Serial EEPROM
Features
■
Functional Description
The CY25C01/02/04/08/16 provides 1024, 2048, 4096, 8192,
and 16384 bits of serial Electrically Erasable and Programmable
Read Only Memory (EEPROM) organized as 128, 256, 512,
1024, or 2048 words of eight bits each. The device is optimized
for use in many industrial applications where low power and low
voltage operations are essential. The CY25C01/02/04/08/16 is
available in space saving 8-Pin SOIC, and 8-Pin TSSOP
packages.
The CY25C01/02/04/08/16 is enabled through the Chip Select
pin (CS) and accessed via a three-wire interface consisting of
Serial Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All programming cycles are completely self timed and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status
register with one of four blocks of write protection. Separate
program enable and program disable instructions are provided
for additional data protection. Hardware data protection is
provided through the WP pin to protect against inadvertent write
attempts to the status register. The HOLD pin can be used to
suspend any serial communication without resetting the serial
sequence.
Continuous voltage operation
❐
V
CC
= 1.8V to 5.5V
Internally organized as 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K), or 2048 x 8 (16K)
Serial peripheral interface compatible
Supports SPI modes 0 (0,0) and 3 (1,1)
Block write protection
❐
Protect 1/4,1/2, or entire array
Fast clock rate
❐
20 MHz clock rate (V
CC
= 4.5V to 5.5V)
❐
10 MHz clock rate (V
CC
= 1.8V to 5.5V)
Write protect (WP) pin and write disable instructions for both
hardware and software data protection
32-byte page write mode
Self timed write cycle (5 ms max)
High reliability
❐
Endurance: 1 million write cycles
❐
Data retention: 100 years
Industrial temperature range
8-Pin SOIC and 8-Pin TSSOP packages
Pb-free and RoHS compliant
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Logic Block Diagram
CS
V
CC
HOLD
SI
CY25C01/02/04/08/16
SO
WP
SCK
V
SS
Cypress Semiconductor Corporation
Document #: 001-15633 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 05, 2009
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CY25C01/02/04/08/16
Pin Configuration
Figure 1. Pin Diagram - 8-Pin SOIC/TSSOP
CS
SO
WP
GND
1
2
3
4
8
7
Top View
(not to scale)
6
5
V
CC
HOLD
SCK
SI
Table 1. Pin Definitions - 8 Pin SOIC/TSSOP
Pin Name
CS
SO
WP
GND
SI
SCK
HOLD
V
CC
8-SOIC/PDIP/TSSOP
Pin Number
1
2
3
4
5
6
7
8
I/O Type
Input
Output
Input
Input
Input
Input
Input
Input
Description
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Data Clock
Suspends Serial Input
Power Supply
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
Serial Interface Description
Master
The device that generates the serial clock.
operations are inhibited. WP going low while CS is still low inter-
rupts a write to the CY25C01/02/04/08/16. If the internal write
cycle is already initiated, WP going low has no effect on the write
operation.
Slave
The CY25C01/02/04/08/16 always operates as a slave because
the Serial Clock pin (SCK) is always an input.
SPI Modes
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the following modes:
■
■
Transmitter or Receiver
The CY25C01/02/04/08/16 has separate pins designated for
data transmission (SO) and reception (SI).
CPOL=0, CPHA=0
CPOL=1, CPHA=1
MSB
The Most Significant Bit (MSB) is the first bit transmitted and
received.
For these two modes, input data is latched in on the rising edge
of Serial Clock (SCK) and output data is available from the falling
edge of Serial Clock (SCK).
The difference between the two modes, shown in
Figure 2
and
Figure 3,
is the clock polarity when the bus master is in standby
mode and not transferring data:
■
■
Serial Op-Code
After the device is selected with CS going low, the first byte is
received. This byte contains the op-code that defines the opera-
tions to be performed.
SCK remains at 0 for (CPOL=0, CPHA=0)
SCK remains at 1 for (CPOL=1, CPHA=1)
Invalid Op-Code
If an invalid op-code is received, no data is shifted to the
CY25C01/02/04/08/16. The serial output pin (SO) remains in a
high impedance state until the falling edge of CS is detected
again. This reinitializes the serial communication.
Figure 2. SPI Mode 0
CS
0
SCK
1
2
3
4
5
6
7
Chip Select
The CY25C01/02/04/08/16 is selected when the CS pin is low.
When the device is not selected, data is not accepted through
the SI pin and the serial output pin (SO) remains in a high
impedance state.
SO
7
MSB
6
5
4
3
2
1
0
LSB
Hold
The HOLD pin is used in conjunction with the CS pin to select
the CY25C01/02/04/08/16. When the device is selected and a
serial sequence is underway, HOLD can be used to pause the
serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought
low when the SCK pin is low. To resume serial communication,
the HOLD pin is brought high when the SCK pin is low (SCK may
still toggle during HOLD). The HOLD signal behaves as a level
sensitive signal. This means, if the HOLD signal is asserted
when SCK is high, its value is latched and when SCK becomes
low, the latched value is considered to halt the transmission.
Inputs to the SI pin are ignored when the SO pin is in the high
impedance state.
Figure 3. SPI Mode 3
CS
0
SCK
1
2
3
4
5
6
7
SO
7
MSB
6
5
4
3
2
1
0
LSB
Write Protect
The write protect pin (WP) enables normal read or write opera-
tions when held high. When the WP pin is brought low, all write
Document #: 001-15633 Rev. *C
Page 3 of 17
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CY25C01/02/04/08/16
Operating Features
Power Up
When the power supply is turned on, V
CC
rises from V
SS
to V
CC
.
During this time, the Chip Select (CS) must be allowed to follow
the V
CC
voltage. It must not be allowed to float, but must be
connected to V
CC
through a suitable pull up resistor. As a built in
safety feature, Chip Select (CS) is edge sensitive and level
sensitive. After power up, the device is not selected until a falling
edge is first detected on Chip Select (CS). This ensures that the
Chip Select (CS) was high, before going low to start the first
operation.
defined). When V
CC
passes over the POR threshold, the device
is reset and is in the following state:
■
■
■
Standby power mode
Deselected (after power up, a falling edge is required on Chip
Select (S) before any instructions are started)
Not in the hold condition
The Write Enable (WEN) bit is reset to 0
(RDY) is set to 1
Status register state:
■
■
Device Internal Reset
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included. During power up
(continuous rise up of V
CC
), the device does not respond to any
instruction until the V
CC
reaches the POR threshold voltage (this
threshold is lower than the minimum V
CC
operating voltage
During power down (continuous decay of V
CC
), as soon as V
CC
drops from the normal operating voltage, below the POR
threshold voltage, the device stops responding to any instruction
sent to it.
The WPEN
[1]
, BP1 and BP0 bits of the status register are
unchanged from the previous power down (they are non volatile
bits). Before selecting and issuing instructions to the memory, a
valid and stable V
CC
voltage must be applied. This voltage must
remain stable and valid until the end of the transmission of the
instruction and for a write instruction, until the completion of the
internal write cycle (t
WR
).
Table 2. Instruction Set
Instruction
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction
Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data From Memory Array
Write Data To Memory Array
Power Down
During power down, the device must be deselected and in
standby power mode (no internal write cycle in progress). Chip
Select (CS) must be allowed to follow the voltage applied on V
CC
.
Active Power and Standby Power Modes
When Chip Select (CS) is low, the device is selected in the active
power mode. The device consumes I
CC
, as specified in
DC Electrical Characteristics
on page 9. When Chip Select (CS)
is high, the device is deselected. If an erase or write cycle is
currently not in progress, the device goes into the standby power
mode, and the device consumption drops to I
SB1
.
Write Enable (WREN)
The device powers up in the write disable state when V
CC
is
applied. All programming instructions must therefore be
preceded by a Write Enable instruction.
Functional Description
The CY25C01/02/04/08/16 supports the SPI bus data trans-
mission protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CY25C01/02/04/08/16 to interface directly with
many of the popular microcontrollers.
The CY25C01/02/04/08/16 uses an 8-bit instruction register. The
list of instructions and their operation codes are contained in
Table 2.
All instructions, addresses, and data are transferred with
the MSB, and it starts with a high to low (CS) transition.
Write Disable (WRDI)
To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI
instruction is independent of the status of the WP pin.
Read Status Register (RDSR)
The Read Status Register instruction provides access to the
status register. The READY/BUSY and Write Enable status of
the device is determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Note
1. WPEN bit is applicable only for 8K and 16K devices.
Document #: 001-15633 Rev. *C
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CY25C01/02/04/08/16
Table 3. Status Register Format for CY25C01/02/04
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 4. Status Register Format for CY25C08/16
Bit 7
WPEN
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 5. Status Register Bit Definition
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Definition
Bit 0 = ‘0’ (RDY) indicates the device is READY. Bit 0 = ‘1’ indicates the write cycle is in progress.
Bit 1= ‘0’ indicates the device is not WRITE ENABLED. Bit 1 = ‘1’ indicates the device is write enabled.
See
Table 6.
See
Table 6.
Bits 4–6 are ‘0’s when device is not in an internal write cycle.
Bit 7 (X / WPEN) When the device is not in an internal write cycle, this bit is 0 in CY25C01/02/04 and WPEN (See
Table 7
on page 5) in CY25C08/16
Bits 0–7 are ‘1’s during an internal write cycle.
Write Status Register (WRSR)
The WRSR instruction enables the user to select one of four
levels of protection. The CY25C01/02/04/08/16 is divided into
four array segments. One quarter, one half, or all of the memory
segments can be protected. Any of the data within any selected
segment is therefore read only. The block write protection levels
and corresponding status register control bits are shown in
Table 6.
The three bits BP0, BP1, and WPEN
[1]
are nonvolatile cells that
have the same properties and functions as the regular memory
cells (for example, WREN, t
WC
, RDSR).
Table 6. Block Write Protect Bits
Level
0
1 (1/4)
2 (1/2)
3 (All)
Table 7. WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
The WRSR instruction in CY25C08/16 also allows the user to
enable or disable the write protect (WP) pin using the Write
Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is ‘1’. Hardware write
protection is disabled when the WP pin is high or when the
WPEN bit is ‘0’ (See
Table 7).
When the device is hardware write protected, writes to the status
register, including the block protect bits and the WPEN
[1]
bit, and
the block protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory that are not
block protected.
Array Addresses Protected
CY25C01
None
60 - 7F
40 - 7F
00 - 7F
CY25C02
None
C0 - FF
80 - FF
00 - FF
CY25C04
None
180 - 1FF
100 - 1FF
000 - 1FF
CY25C08
None
CY25C16
None
0300 - 03FF 0600 - 07FF
0200 - 03FF 0400 - 07FF
0000 - 03FF 0000 - 07FF
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
Document #: 001-15633 Rev. *C
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