PRELIMINARY
CY26210
PacketClock™
T1/E1 to 19.44 MHz Clock Translator
Features
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V Operation
Part Number
CY26210
Outputs
1
Input Frequency Range
1.544 or 2.048 MHz
Benefits
High performance PLL tailored for T1/E1 clock generation
Meets critical timing requirements in complex system designs
Enables application compatibility
Output Frequencies
19.44 MHz
Logic Block Diagram
Fref
Q
Φ
VCO
P
OUTPUT
DIVIDERS
CLK1
PLL
FS
AVDD
AVSS
VDD
VSS
Pin Configuration
CY26210
8-pin SOIC
Fref
AVDD
FS
AVSS
1
2
3
4
8
7
6
5
NC
VSS
CLK1
VDD
Table 1. CY26210 Frequency Select Option
Frequency Select
0
1
Input
1.544
2.048
CLK1
19.44
19.44
Unit
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07446 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
CY26210
Pin Description
Name
Fref
AVDD
FS
AVSS
VDD
CLK1
VSS
NC
Pin Number Description
1
2
3
4
5
6
7
8
1.544 MHz/2.048 MHz Reference Input
Analog Voltage Supply
Frequency Select – See
Table 1
Analog Ground
Voltage Supply
19.44 MHz Clock Output
Ground
Leave floating No Connect
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Description
Supply Voltage
Storage Temperature
[1]
Junction Temperature
Digital Inputs
Digital Outputs referred to V
DD
Electro-Static Discharge
V
SS
– 0.3
V
SS
– 0.3
2000
Min.
–0.5
–65
Max.
7.0
125
125
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
°C
°C
V
V
V
Recommended Operating Conditions
Parameter
V
DD
/AV
DD
T
A
C
LOAD
f
REF
t
PU
Description
Operating Voltage
Ambient Temperature (Commercial)
Max. Load Capacitance
Reference Frequency
Power-up time for all VDD's to reach
minimum specified voltage (power
ramps must be monotonic)
1.544
0.05
Min.
3.135
0
Typ.
3.3
Max.
3.465
70
15
2.048
500
Unit
V
°C
pF
MHz
ms
DC Electrical Specifications (Commercial)
Parameter
I
OH
I
OL
C
IN
I
IZ
I
DD
V
IH
V
IL
Name
Output High Current
Output Low Current
Input Capacitance
Input Current
Supply Current
Input High Voltage
Input Low Voltage
Sum of Core and Output Current
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
0.7V
DD
0.3V
DD
5
20
Description
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
Min.
12
12
Typ.
24
24
7
Max.
Unit
mA
mA
pF
µA
mA
V
V
AC Electrical Specifications (V
DD
= 3.3V)
Parameter
[2]
DC
ERO
EFO
t
9
t
10
Name
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Clock Jitter
PLL Lock Time
Description
Duty Cycle is defined in
Figure 1,
50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, C
LOAD
= 15pF See
Figure 2.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, C
LOAD
= 15pF See
Figure 2.
Peak to Peak Period Jitter
Min
45
0.8
0.8
Typ
50
1.4
1.4
200
3
Max
55
Unit
%
V/ns
V/ns
ps
ms
Page 2 of 5
Document #: 38-07446 Rev. *A
CY26210
AC Electrical Specifications (V
DD
= 3.3V)
Parameter
[2]
Note:
1.
Rated for 10 years
2.
Not 100% tested
Name
Description
Min
Typ
Max
Unit
Test and Measurement Set-up
V
DD
0.1
µF
OUTPUTS
CLK out
C
LOAD
GND
Voltage and Timing Definitions
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
80%
t4
CLK
20%
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x V
DD
/ t3, EF = 0.6 x V
DD
/ t4
Ordering Information
Ordering Code
CY26210SC
CY26210SCT
Package Name
S8
S8
Package Type
8-Pin SOIC
8-Pin SOIC - Tape and Reel
Operating Range
Commercial
Commercial
Operating Voltage
3.3V
3.3V
Document #: 38-07446 Rev. *A
Page 3 of 5
PRELIMINARY
Package Drawing and Dimensions
8-Lead (150-Mil) SOIC S8
CY26210
51-85066-A
Document #: 38-07446 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26210
Document History Page
Document Title: CY26210 PacketClock™ T1/E1 to 19.44 MHz Clock Translator
Document Number: 38-07446
REV.
**
*A
ECN NO.
116739
121904
Issue
Date
09/12/02
12/14/02
Orig. of
Change
CKN
RBI
Description of Change
New data sheet
Power up requirements added to Operating Conditions Information
Document #: 38-07446 Rev. *A
Page 5 of 5
