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CY27022SCT

Clock Generator, 180.6336MHz, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:Cypress(赛普拉斯)

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Cypress(赛普拉斯)
零件包装代码
SOIC
包装说明
0.150 INCH, MS-012, SOIC-8
针数
8
Reach Compliance Code
not_compliant
ECCN代码
EAR99
JESD-30 代码
R-PDSO-G8
JESD-609代码
e0
长度
4.889 mm
湿度敏感等级
1
端子数量
8
最高工作温度
70 °C
最低工作温度
最大输出时钟频率
180.6336 MHz
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
220
主时钟/晶体标称频率
16.9344 MHz
认证状态
Not Qualified
座面最大高度
1.727 mm
最大供电电压
3.63 V
最小供电电压
2.97 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
TIN LEAD
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
3.8985 mm
uPs/uCs/外围集成电路类型
CLOCK GENERATOR, OTHER
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CY27022
Clock Generator for Net-MD System
Features
Description
The CY27022 is a clock generator that integrates clock require-
ments for a Net-MD system.
The CY27022 supports USB clock, Mini Disc, and CPU clock
requirements.
Supports Clock Requirement for Mini Disc
16.9344 MHz Crystal or Clock Input
12.000 MHz for USB Clock Output
10.0352 MHz for Controller Clock Output
90.3168 MHz/180.6336 MHz Selectable Clock Output
Load Capacitance for Crystal (Cl = 12.1 pF Typ)
3.3V Operation
8-pin SOIC Package
Table 1. Frequency Table (Input = 16.9344 MHz)
Pin Number
1
5
5
6
Name
CLKC
CLKB
CLKB
CLKA
Output Frequency
12.000 MHz
90.3168 MHz
180.6336 MHz
10.0352 MHz
FS
x
0
1
x
Pinout
Figure 1. Pin Diagram - 8-Pin SOIC
CLKC
GND
XIN
XOUT
1
2
3
4
SOIC
8
7
6
5
FS
VDD
CLKA
CLKB
Table 2. Pin Definition - 8 SOIC
Pin
Number Pin Name
1
2
3
4
5
6
7
8
CLKC
GND
XIN
XOUT
CLKB
CLKA
VDD
FS
I/O
O
I
O
O
O
I
Description
12.000 MHz clock output
16.9344 MHz reference crystal or external clock input
Reference crystal feedback (float if XIN is driven by external reference clock)
Selectable clock output, see
Table 1.
10.0352 MHz clock output
Frequency selection input pin. This pin controls the frequency presented on CLKB. Internal pull up
PWR Device Ground
PWR +3.3V power supply
Cypress Semiconductor Corporation
Document Number:38-07293 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 10, 2009
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CY27022
Maximum Ratings
The voltage on any input or I/O pin cannot exceed the power pin
during power up. These user guidelines are not tested.
Maximum Input Voltage Relative to GND: .........................–0.3V
Maximum Input Voltage Relative to V
DD
:.................. V
DD
+ 0.3V
Storage Temperature: ........................................ –65° to +150°C
Operating Temperature:.........................................0°C to +70°C
Maximum ESD Protection ................................................... 2KV
Maximum Power Supply:.....................................................5.5V
Operating Voltage: ..................................................... 2.9V–3.6V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
precautions are taken to avoid application of any voltage higher
than the maximum rated voltages to this circuit. For proper
operation, V
in
and V
out
are constrained to the range:
GND < (V
in
or V
out
) < V
DD
Unused inputs are always to an appropriate logic voltage level
(either GND or V
DD
).
DC Parameters
Table 3. DC Parameters
[2]
(V
DD
= 3.3V ±10%, T
A
= 0 to 70°C)
Parameter
V
IL
V
IH
I
IL
IIH
Idd3.3V
V
OL
V
OH
C
XTAL
Description
Input low voltage
Input high voltage
Input low current
Input high current
Dynamic supply current
Output low voltage
Output high voltage
Crystal pin capacitance
Conditions
See
Note 1
See
Note 1
See
Note 1
See
Note 1
No output load, FS = 1 (180-MHz mode)
I
OL
= 4.0 mA
I
OH
= –4.0 mA
XIN, XOUT pin capacitance
2.4
23
19
2.0
–72
-15
10
28
0.4
Min
Typ
Max
0.8
Unit
V
V
μA
μA
mA
V
V
pF
AC Parameters
Table 4. AC Parameters
[3]
Parameter
Tr1
Tf1
Tr2
Tf2
Tpu
Tdc
Tj1
Tj2
Description
Rise time
Fall time
Rise time
Fall time
Power up to stable output
Clock duty cycle
Clock jitter
Clock jitter
Comments
CLKA and CLKC at rated load
[4, 5, 6, 7]
CLKA and CLKC at rated load
[4, 5, 6, 7]
CLKB at rated load
[4, 5, 6, 7]
CLKB at rated load
[4, 5, 6, 7]
All output clocks
[5]
All clocks at rated load
[ 6, 7]
Min
Typ
2
2
Max
3
3
1.5
1.5
3
Unit
ns
ns
ns
ns
ms
%
ps
ps
45
50
55
250
150
CLKA and CLKC at rated load
[4, 5, 6, 7]
CLKB at rated load
[4, 5, 6, 7]
Notes
1. Applicable to input signal: FS. Internal pull up resistor value may vary between 70k and 170k.
2. The voltage on any input or IO pin cannot exceed the power pin during power up.
3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs
4. Measured between 0.2*V
DD
and 0.8*V
DD
Volts.
5. Measured between 0.2*V
DD
and 0.7*V
DD
Volts.
6. Clocks trigger at 1.5 Volts.
7. All outputs have a 15 pF load.
Document Number:38-07293 Rev. *E
Page 2 of 4
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CY27022
Ordering Information
Ordering Code
CY27022SCT
CY27022SXC
CY27022SXCT
Package Type
8-pin SOIC - Tape and Reel
8-pin SOIC (Pb-free)
8-pin SOIC (Pb-free) - Tape and Reel
Operating Range
Commercial (0 to 70°C)
Commercial (0 to 70°C)
Commercial (0 to 70°C)
Operating Voltage
3.3V±10%
3.3V±10%
3.3V±10%
Package Drawing and Dimensions
Figure 2. 8-Pin (150-Mil) SOIC
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
0.150[3.810]
0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
8
SZ08.15 LEAD FREE PKG.
0.189[4.800]
0.196[4.978]
SEATING PLANE
0.010[0.254]
0.016[0.406]
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document Number:38-07293 Rev. *E
Page 3 of 4
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CY27022
Document History
Document Title: CY27022 Clock Generator for Net-MD System
Document Number: 38-07293
REV.
**
*A
*B
*C
ECN NO.
116146
122884
406494
1191263
Submission
Date
08/14/02
12/22/02
See ECN
See ECN
Orig. of
Change
OSM
RBI
XHT/CFT
KVM
New Data Sheet
Added power up requirements to Maximum Ratings
Obsolete specification. Sunset Review Clean up. Personalized clock chips for
Japanese customer and no longer in use.
Revived the data sheet as the device is still active. Added Pb-free part
numbers. Updated note 2 to remove mention of multiple supplies and voltage
sequencing. Replaced instances of VSS with GND.
Posting to external web.
Description of Change
*D
*E
2710266
2748211
05/22/09
08/10/09
KVM/PYRS Remove obsolete part number from Ordering Information table: CY27022SC
TSAI
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at
cypress.com/sales.
Products
PSoC
Clocks & Buffers
Wireless
Memories
Image Sensors
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
© Cypress Semiconductor Corporation, 2002-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number:38-07293 Rev. *E
Revised August 10, 2009
Page 4 of 4
All products and company names mentioned in this document may be the trademarks of their respective holders.
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参数对比
与CY27022SCT相近的元器件有:CY27022SXC。描述及对比如下:
型号 CY27022SCT CY27022SXC
描述 Clock Generator, 180.6336MHz, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8 Clock Generator, 180.6336MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
是否Rohs认证 不符合 符合
零件包装代码 SOIC SOIC
包装说明 0.150 INCH, MS-012, SOIC-8 0.150 INCH, LEAD FREE, MS-012, SOIC-8
针数 8 8
Reach Compliance Code not_compliant unknown
ECCN代码 EAR99 EAR99
JESD-30 代码 R-PDSO-G8 R-PDSO-G8
JESD-609代码 e0 e3
长度 4.889 mm 4.889 mm
湿度敏感等级 1 3
端子数量 8 8
最高工作温度 70 °C 70 °C
最大输出时钟频率 180.6336 MHz 180.6336 MHz
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SOP SOP
封装形状 RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE
峰值回流温度(摄氏度) 220 260
主时钟/晶体标称频率 16.9344 MHz 16.9344 MHz
认证状态 Not Qualified Not Qualified
座面最大高度 1.727 mm 1.727 mm
最大供电电压 3.63 V 3.63 V
最小供电电压 2.97 V 2.97 V
标称供电电压 3.3 V 3.3 V
表面贴装 YES YES
技术 CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL
端子面层 TIN LEAD Matte Tin (Sn)
端子形式 GULL WING GULL WING
端子节距 1.27 mm 1.27 mm
端子位置 DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED 20
宽度 3.8985 mm 3.8985 mm
uPs/uCs/外围集成电路类型 CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
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