The CY28400 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
DIFT1
OE_(1,6)
SRC_STOP#
PWRDWN#
Output
Control
DIFC1
DIFT2
SCLK
SDATA
SMBus
Controller
Output
Buffer
DIFC2
PLL/BYPASS#
SRCT_IN
SRCC_IN
DIFT5
DIFC5
VDD
SRCT_IN
SRCC_IN
VSS
VDD
DIFT1
DIFC1
OE_1
DIFT2
DIFC2
VDD
PLL/BYPASS#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD_A
VSS_A
IREF
VSS
VDD
DIFT6
DIFC6
0E_6
DIFT5
DIFC5
VDD
HIGH_BW#
SRC_STOP#
PWRDWN#
28 SSOP
DIV
HIGH_BW#
DIFT6
DIFC6
CY28400
PLL
Cypress Semiconductor Corporation
Document #: 38-07591 Rev. *A
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 1, 2005
CY28400
Pin Descriptions
Pin
2,3
6,7,9,10,19,20,22,23
8,21
Name
SRCT_IN, SRCC_IN
DIFT/C(2:1) & (6:5)
OE_1, OE_6
Type
I,DIF
O,DIF
I,SE
Description
0.7V differential SRC inputs from the clock synthesizer
0.7V differential clock outputs
3.3V LVTTL active LOW input for three-stating differential
outputs
(DIFT2 and DIFT5 are unaffected by the assertion of OE
inputs)
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL input for SRC_STOP#, active LOW
3.3V LVTTL input for Power Down, active LOW
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential
output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V power supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
17
16
15
13
14
26
12
28
27
4,25
1,5,11,18,24
HIGH_BW#
SRC_STOP#
PWRDWN#
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
I,SE
I,SE
I,SE
I,SE
I/O,OC
I
I
3.3V
GND
3.3V
GND
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition
Bit
7
(6:0)
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Description
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Description
Bit
1
2:8
9
10
11:18
19
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Block Read Protocol
Description
Document #: 38-07591 Rev. *A
Page 2 of 13
CY28400
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
20:27
28
29:36
37
38:45
46
....
....
....
....
Description
Byte Count from master – 8 bits
Acknowledge from slave
Data byte 0 from master – 8 bits
Acknowledge from slave
Data byte 1 from master – 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N – 8 bits
Acknowledge from slave
Stop
Bit
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from host
Data byte 0 from slave – 8 bits
Acknowledge from host
Data byte 1 from slave – 8 bits
Acknowledge from host
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Acknowledge from host
Stop
Block Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
@Pup
0
0
0
0
0
1
HIGH_BW#
Name
Description
PWRDWN# drive mode
0 = Driven when stopped, 1 = Three-state
SRC_STOP# drive mode
0 = Driven when stopped, 1 = Three-state
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
Page 3 of 13
Document #: 38-07591 Rev. *A
CY28400
Byte 0: Control Register 0
(continued)
Bit
1
0
@Pup
1
1
Name
PLL/Bypass#
Description
PLL/Bypass#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV/2
0 = Divided by 2 mode,1 = Normal (output = input)
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
DIFT/C2
DIFT/C1
DIFT/C6
DIFT/C5
Name
Reserved
DIFT/C6 Output Enable
0 = Disabled (three-state), 1 = Enabled
DIFT/C5 Output Enable
0 = Disabled (three-state), 1 = Enabled
Reserved
Reserved
DIFT/C2 Output Enable
0 = Disabled (three-state), 1 = Enabled
DIFT/C1 Output Enable
0 = Disabled (three-state), 1 = Enabled
Reserved
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Allow Control DIFT/C6 with assertion of SRC_STOP#
0 = Free-running, 1 = Stopped with SRC_STOP#
Allow Control DIFT/C5 with assertion of SRC_STOP#
0 = Free-running, 1 = Stopped with SRC_STOP#
Reserved
Reserved
Allow Control DIFT/C2 with assertion of SRC_STOP#
0 = Free-running, 1 = Stopped with SRC_STOP#
Allow Control DIFT/C1 with assertion of SRC_STOP#
0 = Free-running, 1 = Stopped with SRC_STOP#
Reserved
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Document #: 38-07591 Rev. *A
Page 4 of 13
CY28400
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
meet all AC and DC parameters. This means no glitches,
frequency shifting or amplitude abnormalities among others.
Description
PWRDWN# Clarification
[1]
The PWRDWN# pin is used to shut off all clocks cleanly and
instruct the device to evoke power savings mode. Additionally,
PWRDWN# should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. PWRDWN# is an asynchronous active LOW input.
This signal is synchronized internal to the device prior to
powering down the clock buffer. PWRDWN# is an
asynchronous input for powering up the system. When
PWRDWN# is asserted LOW, all clocks will be held HIGH or
three-stated (depending on the state of the control register
drive mode and OE bits) prior to turning off the VCO. All clocks
will start and stop without any abnormal behavior and must
PWRDWN#—Assertion
When PWRDWN# is sampled LOW by two consecutive rising
edges of DIFC, all DIFT outputs will be held HIGH or
three-stated (depending on the state of the control register
drive mode and OE bits) on the next DIFC HIGH-to-LOW
transition. When the SMBus power-down drive mode bit is
programmed to ‘0’, all clock outputs will be held with the DIFT
pin driven HIGH at 2 x Iref and DIFC three-state. However, if
the control register PWRDWN# drive mode bit is programmed
to ‘1’, then both DIFT and the DIFC are three-stated.
PWRDWN#
DIFT
DIFC
Figure 1. PWRDWN# Assertion Diagram
Note:
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches
