2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Features
•
•
•
•
•
•
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
60 ps typical output-to-output skew
Dual or single supply operation:
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
• Pin compatible with MPC940L, MPC9109
• Available in Commercial and Industrial temperature
• 32-pin LQFP package
Description
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50Ω series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
Block Diagram
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
0
1
VDDC
Pin Configuration
VDDC
VSS
25
Q0
Q1
Q2
Q3
28
Q4
27
Q5
26
31
30
32
29
18
Q0-Q17
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
CY29940
10
11
12
13
14
15
16
9
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
Pin Description
[1]
Pin
5
6
3
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
4
8, 16, 29
7, 21
1, 2, 12, 17, 25
Name
PECL_CLK
PECL_CLK#
TCLK
Q(17:0)
VDDC
PWR
I/O
I, PU
I, PD
I, PD
O
PECL Input Clock
PECL Input Clock
External Reference/Test Clock Input
Clock Outputs
Description
TCLK_SEL
VDDC
VDD
VSS
I, PD
Clock Select Input. When LOW, PECL clock is selected and when HIGH
TCLK is selected.
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
Common Ground
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-up
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 4, 2006
[+] Feedback
VDDC
Q17
Q16
Q15
Q14
Q13
Q12
CY29940
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
: ............ V
SS
– 0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD Protection............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
DC Parameters
[2]
:
V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDC
= 3.3V ±5% or 2.5V ±5%, T
A
= –40°C to +85°C
Parameter
V
IL
V
IH
I
IL
I
IH
V
PP
Description
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input
Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
Output Low Voltage
[5, 6, 7]
Output High Voltage
[5, 6, 7]
Quiescent Supply
Current
Dynamic Supply
Current
V
DD
= 3.3V, Outputs @ 150 MHz,
CL = 15 pF
V
DD
= 3.3V, Outputs @ 200 MHz,
CL = 15 pF
V
DD
= 2.5V, Outputs @ 150 MHz,
CL = 15 pF
V
DD
= 2.5V, Outputs @ 200 MHz,
CL = 15 pF
Z
out
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
I
OL
= 20 mA
I
OH
= –20 mA, V
DDC
= 3.3V
I
OH
= –20 mA, V
DDC
= 2.5V
I
DDQ
I
DD
500
Conditions
Min.
V
SS
2.0
Typ.
–
–
–
–
–
Max.
0.8
V
DD
–200
200
1000
Unit.
V
V
µA
µA
mV
V
CMR
V
OL
V
OH
V
DD
– 1.4
V
DD
– 1.0
–
2.4
1.8
–
–
–
–
–
8
10
–
–
–
–
–
–
5
285
335
200
240
12
15
4
V
DD
– 0.6
V
DD
– 0.6
0.5
–
–
7
–
–
–
–
16
20
–
V
V
V
V
V
mA
mA
Ω
pF
Notes:
2.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines
5. Outputs driving 50Ω transmission lines.
6. See
Figure 1
&2.
7. 50% input duty cycle.
Document #: 38-07283 Rev. *C
Page 2 of 7
[+] Feedback
CY29940
AC Parameters
[8]
:
V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDC
= 3.3V ±5% or 2.5V ±5%, T
A
= –40°C to +85°C
Parameter
F
max
t
PD
Description
Input Frequency
PECL_CLK to Q Delay
</=150 MHz
[5, 6, 11]
Conditions
–
V
DD
= 3.3V
85°C
V
DD
= 3.3V
70°C
V
DD
= 2.5V
85°C
V
DD
= 2.5V
70°C
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
Min.
–
2.0
2.1
1.9
2.0
2.5
2.6
2.5
2.6
1.9
2.0
1.8
1.8
2.5
2.5
2.3
2.3
–
–
–
–
–
–
–
–
–
–
–
0.3
0.3
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
60
–
–
–
–
–
–
–
–
Max.
200
3.2
3.4
3.1
3.2
5.2
5
5
5
3
3.2
2.9
3.1
4
4
3.8
3.8
10
55
60
150
200
1.4
2.2
1.2
1.7
850
750
1.1
1.2
Unit.
MHz
ns
t
PD
LVCMOS to Q Delay
</=150 MHz
[5, 6, 11]
V
DD
= 3.3V
85°C
V
DD
= 3.3V
70°C
V
DD
= 2.5V
85°C
V
DD
= 2.5V
70°C
ns
t
J
FoutDC
T
skew
T
skew
(pp)
T
skew
(pp)
T
skew
(pp)
t
R
/t
F
Total Jitter
Output Duty Cycle
[5, 6, 7]
Output-to-Output Skew
[5, 6]
Part-to-Part Skew
[9]
Part-to-Part
Skew
[9]
V
DD
= 3.3V @ 150MHz
FCLK < 134 MHz
FCLK > 134 MHz
V
DD
= 3.3V
V
DD
= 2.5V
PECL, V
DDC
= 3.3V
PECL, V
DDC
= 2.5V
TCLK, V
DDC
= 3.3V
TCLK, V
DDC
= 2.5V
PECL_CLK
TCLK
ps
%
ps
ns
ns
ps
ns
Part to Part Skew
[10]
Output Clocks Rise/Fall Time
[5, 6]
0.7V to 2.0V,
V
DDC
= 3.3V
0.5V to 1.8V,
V
DDC
= 2.5V
Notes:
8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
9. Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew
