CY29948
2.5 V or 3.3 V, 200-MHz,
1:12 Clock Distribution Buffer
2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer
Features
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Description
The CY29948 is a low-voltage 200-MHz clock distribution buffer
with the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The 12 outputs are LVCMOS or LVTTL compatible
and can drive 50
series or parallel terminated transmission
lines. For series terminated transmission lines, each output can
drive one or two traces giving the device an effective fanout of
1:24. The outputs can also be three-stated via the three-state
input TS#. Low output-to-output skews make the CY29948 an
ideal clock distribution buffer for nested clock trees in the most
demanding of synchronous systems.
The CY29948 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
2.5 V or 3.3 V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output three-state control
150 ps typical output-to-output skew
Pin compatible with MPC948, MPC948L, MPC9448
Available in Commercial and Industrial temp. range
32-pin TQFP package
Block Diagram
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
0
1
VDDC
12
Q0-Q11
Pin Configuration
Q0
VDDC
Q2
VDDC
27
26
VSS
Q1
VSS
Q3
25
24
23
22
21
20
19
18
17
32
31
30
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
29
28
CY29948
9
10
11
12
13
14
15
16
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
VSS
Q9
VDDC
Q10
VDDC
Q8
VSS
Q11
Cypress Semiconductor Corporation
Document Number: 38-07288 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 2, 2011
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CY29948
Pin Description
[1]
Pin
3
4
2
9, 11, 13, 15,
17, 19, 21, 23,
25, 27, 29, 31
1
5
6
10, 14, 18, 22,
26, 30
7
8, 12, 16, 20,
24, 28, 32
Name
PECL_CLK
PECL_CLK#
TCLK
Q(11:0)
PWR
–
–
–
VDDC
I/O
I, PU
PECL Input Clock
I, PD
PECL Input Clock
I, PU
External Reference/Test Clock Input
O
Clock Outputs
Description
TCLK_SEL
SYNC_OE
TS#
VDDC
VDD
VSS
–
–
–
–
–
–
I, PU
Clock Select Input.
When LOW, PECL clock is selected. When HIGH
TCLK is selected.
I, PU
Output Enable Input.
When asserted HIGH, the outputs are enabled.
When set LOW the outputs are disabled in a LOW state.
I, PU
Three-state Control Input.
When asserted LOW, the output buffers
are three-stated. When set HIGH, the output buffers are enabled.
–
–
–
2.5 V or 3.3 V Power Supply for Output Clock Buffers
2.5 V or 3.3 V Power Supply
Common Ground
Output Enable/Disable
The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When
SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown
in
Figure 1.
Figure 1. SYNC_OE Timing Diagram
TCLK
SYNC_OE
Q
Note
1. PD = Internal pull-down, PU = Internal pull-up.
Document Number: 38-07288 Rev. *E
Page 2 of 10
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CY29948
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
............. V
SS
– 0.3 V
Maximum Input Voltage Relative to V
DD
............. V
DD
+ 0.3 V
Storage Temperature ............................... –65 °C to + 150 °C
Operating Temperature............................... –40 °C to +85 °C
Maximum ESD protection............................................... 2 kV
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
in
and V
out
should be constrained to the range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= V
DDC
= 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range.
Parameter
V
IL
Description
Input Low Voltage
Conditions
V
DD
= 3.3 V, PECL_CLK single ended
V
DD
= 2.5 V, PECL_CLK single ended
All other inputs
V
IH
Input High Voltage
V
DD
= 3.3 V, PECL_CLK single ended
V
DD
= 2.5 V, PECL_CLK single ended
All other inputs
I
IL
I
IH
V
PP
V
CMR
V
OL
V
OH
I
DDQ
I
DD
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
Output Low Voltage
[5]
Output High Voltage
[5]
Quiescent Supply Current
Dynamic Supply Current
V
DD
= 3.3 V, Outputs @ 100 MHz,
C
L
= 30 pF
V
DD
= 3.3 V, Outputs @ 160 MHz,
C
L
= 30 pF
V
DD
= 2.5 V, Outputs @ 100 MHz,
C
L
= 30 pF
V
DD
= 2.5 V, Outputs @ 160 MHz,
C
L
= 30 pF
Z
out
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
I
OL
= 20 mA
I
OH
= –20 mA, V
DD
= 3.3 V
I
OH
= –20 mA, V
DD
= 2.5 V
Min
1.49
1.10
V
SS
2.135
1.75
2.0
–
–
300
V
DD
– 2.0
V
DD
– 1.2
–
2.5
1.8
–
–
–
–
–
12
14
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
180
270
125
190
15
18
4
Max
1.825
1.45
0.8
2.42
2.0
V
DD
–100
100
1000
V
DD
– 0.6
V
DD
– 0.6
0.4
–
–
7
–
–
–
–
18
22
–
pF
mA
mA
V
V
mV
V
µA
V
Unit
V
Notes
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
CMR
range
and the input lies within the V
PP
specification.
5. Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
Document Number: 38-07288 Rev. *E
Page 3 of 10
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CY29948
AC Parameters
[6]
V
DD
= V
DDC
= 3.3 V ± 10% or 2.5 V ± 5%, over the specified operating range.
Parameter
F
max
T
pd
Description
Input Frequency
[7]
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
F
outDC
t
pZL
, t
pZH
t
pLZ
, t
pHZ
T
skew
T
skew(pp)
T
s
T
h
T
r
/T
f
[7]
Conditions
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
Measured at V
DD
/2
Min
–
–
4.0
4.4
6.0
6.4
45
2
2
–
Typ
–
–
–
–
–
–
–
–
–
150
–
–
–
–
–
–
–
–
Max
200
170
8.0
8.9
10.0
10.9
55
10
10
250
1.5
2.0
–
–
–
–
1.0
1.3
Unit
MHz
ns
Output Duty Cycle
[7, 8, 9]
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Output-to-Output Skew
[7, 9]
Part-to-Part Skew
[10]
Set-up Time
[7, 11]
Hold Time
[7, 11]
Output Clocks Rise/Fall Time
[9]
%
ns
ns
ps
ns
ns
ns
ns
PECL_CLK to Q
TCLK to Q
SYNC_OE to PECL_CLK
SYNC_OE to TCLK
PECL_CLK to SYNC_OE
TCLK to SYNC_OE
0.8 V to 2.0 V, V
DD
= 3.3 V
0.6 V to 1.8 V, V
DD
= 2.5 V
–
–
1.0
0.0
0.0
1.0
0.20
0.20
Figure 2. LVCMOS_CLK CY29948 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
CY29948 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
VTT
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50 transmission lines.
8. 50% input duty cycle.
9. See
Figure 2
and
Figure 3 on page 5.
10. Part-to-Part skew at a given temperature and voltage.
11. Setup and hold times are relative to the falling edge of the input clock.
Document Number: 38-07288 Rev. *E
Page 4 of 10
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CY29948
Figure 3. PECL_CLK CY29948 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29948 DUT
Zo = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 4. Propagation Delay (t
PD
) Test Reference
PEC L_C LK
PEC L_C LK
V
PP
V
CMR
VCC
Q
V C C /2
t
PD
GND
Figure 5. LVCMOS Propagation Delay (t
PD
) Test Reference
LVCMOS_CLK
VCC
VCC /2
GND
VCC
Q
VCC /2
t
PD
GND
Figure 6. Output Duty Cycle (F
outDC
)
VCC
t
P
T0
DC = tP / T0 x 100%
VCC /2
GND
Document Number: 38-07288 Rev. *E
Page 5 of 10
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