CY2XP304
High-Frequency Programmable PECL
Clock Generation Module
Features
• 40 ps typical peak-peak period jitter at 125 MHz
• 30 ps typical output-output skew at 400 MHz
• Four low-skew LVPECL outputs
• Phase-locked loop (PLL) multiplier select
• Serially-configurable multiply ratios
• Eight-bit feedback counter and six-bit reference
counter for high accuracy
• HSTL inputs—HSTL-to-LVPECL level translation
• 125- to 500-MHz output range for high-speed
applications
• High-speed PLL bypass mode to 1.5 GHz
• 36-VFBGA, 6 × 8 × 1 mm
• 3.3V operation
Block Diagram
PLL_MULT
CLK0
CLK0B
CLK1
XIN
XOUT
SER CLK
SER DATA
INA
INAB
CLK_SEL
XTAL
OSCILLATOR
PLL
xM
0
1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
Pin Configuration
C Y 2 X P 3 0 4 3 6 V F B G A P IN C O N F IG U R A T IO N
T O P V IE W
CLK0
CLK0B
CLK1
CLK1B
CLK 2
CLK 2B
CLK3
CLK3B
6
5
V DDA
G ND
T O P V IE W
G ND
G ND
G ND
V DDA
4
G ND
S ER _ D
A TA
V DDB
V DDA
Xout
3
S ER _ C L
K
G ND
G ND
V DDB
NC
2
X in
G ND
G ND
V DDA
V DDB
1
A
V DDB
G ND
PL L _ M U
LT
CLK_SE
L
IN A
IN A B
V DDA
B
C
D
E
F
G
H
Cypress Semiconductor Corporation
Document #: 38-07589 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 27, 2005
CY2XP304
Pin Definitions
Pin #
A1,B1,G3,G4
A2
A3
A4,B2,C1,C3,C4,F3,F4,G2,G5,B5
A5,H1,H2,H4,H5
A6
B6
C6
D6
E6
F6
G6
H6
B3
B4
D1
E1
F1,G1
H3
Pin Name
VDDB
XIN
XOUT
GND
VDDA
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
Reference Crystal Input
Reference Crystal Feedback
Ground
3.3V Power Supply
LVPECL Clock Output
LVPECL Clock Output
(Complement)
LVPECL Clock Output
LVPECL Clock Output
(Complement)
LVPECL Clock Output
LVPECL Clock Output
(Complement)
LVPECL Clock Output
LVPECL Clock Output
(Complement)
Pin Description
3.3V Power Supply for Crystal Driver
SER_CLK
Serial Interface Clock
SER_DATA
Serial Interface Data
PLL_MULT
PLL Multiplier Select Input,
Internal pull-up resistor, see
Frequency Table
CLK_SEL
INA,INAB
NC
Clock Select Input, Internal Pull down.
HIGH select INA/INAB, Internal PLL
is bypassed. LOW select internal PLL
Differential Clock Input pair,
used in PLL-bypassed mode
No Connect
Frequency Table
PLL_Mult
0
1
M (PLL Multiplier)
x16
x8
Example Input Crystal Frequency
25 MHz
31.25 MHz
15.625 MHz
CLK[0:3],CLKB[0:3]
400 MHz
500 MHz
125 MHz
CY2XP304 Two-Wire Serial Interface
Introduction
The CY2XP304 has a two-wire serial interface designed for
data transfer operations, and is used for programming the P
and Q values for frequency generation. S
clk
is the serial clock
line controlled by the master device. S
data
is a serial bidirec-
tional data line. The CY2XP304 is a slave device and can
either read or write information on the dataline upon request
from the master device.
Figure 1
shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled HIGH by a pull-up resistor.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the S
data
LOW before the S
clk
rising edge and hold it
LOW until the S
clk
falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is one byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2
shows the serial interface transfer format used with
the CY2XP304. Two dummy bytes must be transferred before
the first data byte. The CY2XP304 has only three bytes of
latches to store information, and the third byte of data is
reserved. Extra data will be ignored.
Serial Interface Specifications
Figure 2
shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the S
data
from HIGH to LOW while the S
clk
is at
HIGH. Similarly, stop (P) is defined as switching the S
data
from
LOW to HIGH while holding the S
clk
HIGH. Between these two
signals, data on S
data
is synchronous with the clock on the S
clk
.
Document #: 38-07589 Rev. *D
Page 2 of 11
CY2XP304
R
p
R
p
V
DD
S
d a ta
S
clk
S
c lk
_ C
S
d ata
_ C
S
d ata
_ C
S
clk
_ in
S
d ata
_ in
S
clk
_ in
S
d ata
_ in
M a s te r D e vic e
S lav e D ev ice
Figure 1. Device Connections
S
clk
S
data
Start (S)
valid data
Acknowledge
Stop (P)
Figure 2. Serial Interface Specifications
1 bit
7 bits
Slave Address
1 bit
R/W
1 bit
8 bits
Dummy Byte 0
1 bit
8 bits
1 bit
8 bits
1 bit
S
Ack
Ack
Dummy Byte 1
Ack
Data 0
Ack
Data 1
8 bits
Ack
1 bit
P
Figure 3. CY2XP304 Transfer Format
Serial Interface Address for the CY2XP304
A6
1
A5
1
A4
0
A3
0
A2
1
A1
0
A0
1
R/W
0
Serial Interface Programming for the CY2XP304
b7
Data0
Data1
Data2
QCNTBYP
P<7>
Reserved
b6
SELPQ
P<6>
Reserved
b5
Q<5>
P<5>
Reserved
b4
Q<4>
P<4>
Reserved
b3
Q<3>
P<3>
Reserved
b2
Q<2>
P<2>
Reserved
b1
Q<1>
P<1>
Reserved
b0
Q<0>
P<0>
Reserved
To program the CY2XP304 using the two-wire serial interface,
set the SELPQ bit HIGH. The default setting of this bit is LOW.
The P and Q values are determined by the following formulas:
P
final
= (P
7..0
+ 3) * 2
Q
final
= Q
5..0
+ 2
If the QCNTBYP bit is set HIGH, then Q
final
defaults to a value
of 1. The default setting of this bit is LOW.
If the SELPQ bit is set LOW, the PLL multipliers will be set
using the values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q
values for stable PLL operation. This software is downloadable
from www.cypress.com.
Document #: 38-07589 Rev. *D
Page 3 of 11
CY2XP304
PLL Frequency = Reference x P/Q = Output
Reference
Q
Φ
VCO
P
Output
PLL
Figure 4. PLL Block Diagram
Functional Specifications
Crystal Input
The CY2XP304 receives its reference from an external crystal.
Pin XIN is the reference crystal input, and pin XOUT is the
reference crystal feedback. The parameters for the crystal are
given on page 5 of this data sheet. The oscillator circuit
requires external capacitors. Please refer to the application
note entitled
Crystal Oscillator Topics
for details.
Select Input
There are two select input pins, the PLL_MULT and CLK_SEL.
PLL_MULT pin selects the frequency multiplier in the PLL, and
is a standard LVCMOS input. The S pin has an internal pull-up
resistor. The multiplier selection is given on page 2 of this data
sheet (see
Frequency Table).
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For V
DD
and V
DDX
any
sequences are allowed to power-up and power-down the
CY2XP304.
State Transition Characteristics
From
To
Transition
Latency
3 ms
Description
Time from V
DD
/V
DDX
is
applied and settled to
CLK/CLKB outputs
settled.
V
DD
/V
DDX
CLK/CLK
On
B Normal
Document #: 38-07589 Rev. *D
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CY2XP304
Absolute Maximum Conditions
Parameter
V
CC
V
CC
VTT
V
IN
V
OUT
LU
I
T
S
T
A
T
J
Ø
Jc
Ø
Ja
ESD
h
M
SL
G
ATES
Description
Supply Voltage
Operating Voltage
Output Termination Voltage
Input Voltage
Output Voltage
Latch Up Immunity
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Moisture Sensitivity Level
Total Functional Gate Count
Assembled die
Condition
Non-functional
Functional
Relative to V
CC
Relative to V
CC
Functional
Non-functional
Functional
Non-functional
Functional
Functional
–65
–40
–
11.38
85.83
2000
3
50
[1]
[1]
Min.
–0.3
3.135
V
CC
– 2
–0.3
–0.3
100
Max.
4.6
3.465
V
CC
+ 0.3
V
CC
+ 0.3
+150
+85
150
Unit
V
V
V
V
V
mA
°C
°C
°C
°C/W
°C/W
V
N.A.
Ea.
Relative to V
CC[1]
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled
Crystal Oscillator Topics
for details.
Crystal Requirements
Parameter
X
F
Frequency
Description
Min.
10
Max.
31.25
Unit
MHz
DC Electrical Specifications
Parameter
V
DD
V
IL
V
IH
R
PUP
t
PU
Supply voltage
Input signal low voltage at pin PLL_MULT
Input signal high voltage at pin PLL_MULT
Internal pull-up resistance
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min.
3.135
–
0.65
10
0.05
Max.
3.465
0.35
–
100
500
Unit
V
V
V
kΩ
ms
Operating Conditions
Parameter
T
A
Industrial Temperature
Note:
1. Where V
CC
is 3.3V±5%.
Description
Commercial Temperature
Min.
0
–40
Max.
70
85
Unit
°C
°C
Document #: 38-07589 Rev. *D
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