organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), and active LOW output enable (OE)
and three-state drivers. Both devices have an automatic
power-down feature (CE
1
), reducing the power consumption
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
Temperature ranges:
❐
Commercial: 0 °C to 70 °C
❐
Industrial: –40 °C to 85 °C
❐
Automotive-A: –40 °C to 85 °C
High speed
❐
55 ns
CMOS for optimum speed/power
Easy memory expansion with CE
1
, CE
2
and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Available in Pb-free 28-pin SNC package
■
■
■
■
■
■
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 27, 2011
CY6264
Pin Configuration
Selection Guide
Description
Maximum access time
Maximum operating current
Commercial
Industrial
Automotive-A
Maximum CMOS standby current
Commercial
Industrial
Automotive-A
Range
–55
55
100
260
–
15
30
–
–70
70
100
200
200
15
30
30
Unit
ns
mA
mA
mA
mA
mA
mA
Document #: 001-02367 Rev. *C
Page 2 of 12
CY6264
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................. –65
°C
to +150°C
Ambient temperature with
power applied ........................................... –55
°C
to +125
°C
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z state
[1]
............................................–0.5 V to +7.0 V
DC input voltage
[1]
........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Automotive-A
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
V
CC
5 V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
[1]
Input leakage current
Output leakage current
V
CC
operating
supply current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, output disabled
V
CC
= Max, I
OUT
= 0 mA
Commercial
Industrial
Automotive-A
I
SB1
Automatic CE
1
power-down current
Max V
CC
, CE
1
≥
V
IH,
Min duty cycle=100%
Commercial
Industrial
Automotive-A
I
SB2
Automatic CE
1
power-down current
Max V
CC
, CE
1
≥
V
CC
– 0.3 V, Commercial
V
IN
≥
V
CC
– 0.3 V or V
IN
≤
0.3 V
Industrial
Automotive-A
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
2.2
–0.5
–5
–5
–
–
–
–
–
–
–
–
–
15
30
20
50
–55
Min
2.4
0.4
V
CC
0.8
+5
+5
100
260
2.2
–0.5
–5
–5
–
–
–
–
–
–
–
–
–
Max
Min
2.4
0.4
V
CC
0.8
+5
+5
100
200
200
20
40
40
15
30
30
mA
mA
–70
Max
Unit
V
V
V
V
μA
μA
mA
Capacitance
Parameter
[2]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25
°C,
f = 1 MHz,
V
CC
= 5.0 V
Max
7
7
Unit
pF
pF
Notes
1. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-02367 Rev. *C
Page 3 of 12
CY6264
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
Ω
5V
OUTPUT
R2
255
Ω
5 pF
INCLUDING
JIG AND
SCOPE
R1 481
Ω
ALL INPUT PULSES
3.0 V
R2
255
Ω
GND
10%
90%
90%
10%
≤
5 ns
≤
5 ns
(a)
(b)
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
167
Ω
1.73 V
Switching Characteristics
Over the Operating Range
Parameter
[3]
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
WRITE CYCLE
[6]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write cycle time
CE
1
LOW to write end
CE
2
HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high
Z
[4]
WE HIGH to low Z
50
40
30
40
0
0
25
25
0
–
5
–
–
–
–
–
–
–
–
–
20
–
70
60
50
55
0
0
40
35
0
–
5
–
–
–
–
–
–
–
–
–
30
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address to data valid
Data hold from address change
CE
1
LOW to data valid
CE
2
HIGH to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
[4]
CE
1
LOW to low Z
[5]
CE
2
HIGH to low Z
CE
1
HIGH to high Z
[4, 6]
CE
2
LOW to high Z
CE
1
LOW to power-up
CE
1
HIGH to power-down
55
–
5
–
–
–
3
–
5
3
–
0
–
20
–
–
20
–
25
55
40
25
–
55
70
–
5
–
–
–
5
–
5
5
–
0
–
–
70
–
70
70
35
–
30
–
–
30
–
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
–55
Min
Max
Min
–70
Max
Unit
Notes
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
4. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
5. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
for any device.
6. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
