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CY74FCT163LDH373PAC

Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48

器件类别:逻辑    逻辑   

厂商名称:Cypress(赛普拉斯)

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器件参数
参数名称
属性值
是否Rohs认证
不符合
零件包装代码
TSSOP
包装说明
0.240 INCH, 0.0196 INCH PITCH, TSSOP-48
针数
48
Reach Compliance Code
not_compliant
其他特性
BUS HOLD I/P'S
系列
FCT
JESD-30 代码
R-PDSO-G48
JESD-609代码
e0
长度
12.5 mm
负载电容(CL)
30 pF
逻辑集成电路类型
BUS DRIVER
最大I(ol)
0.006 A
位数
8
功能数量
2
端口数量
2
端子数量
48
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP48,.3,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源
3/3.3 V
Prop。Delay @ Nom-Sup
8 ns
传播延迟(tpd)
13 ns
认证状态
Not Qualified
座面最大高度
1.1 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
宽度
6.1 mm
Base Number Matches
1
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fax id: 7050
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
16-Bit Latch
Features
• Low power, pin-compatible replacement for LCX, LPT,
LVC, LVCH & LVT families
• 5V tolerant inputs and outputs*
• 6 mA & 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.2 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40°C to +85°C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical
V
olp
(ground bounce) performance exceeds Mil
Std 883D
• V
CC
= 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H373
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• *Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
CY74FCT163LD2373
• Lite Drive™ option for low noise applications
• 6 mA balanced drive outputs
• FCT-A speed at 5.2 ns
• V
CC
= 3.0V to 3.6V
• ESD (HBM) > 1100V
Functional Description
These devices are 16-bit, D-type latches, designed for use in
bus applications requiring high speed and low power. They can
either be used as two independent 8-bit latches, or as a single
16-bit latch by connecting the Output Enable (OE) and Latch
(LE) inputs. The outputs are 24-mA balanced output drivers
with current limiting resistors to reduce the need for external
terminating resistors and provide for minimal undershoot and
reduced ground bounce. Flow-through pinout and small shrink
packaging aid in simplifying board layout.
The CY74FCT163H373 and CY74FCT163LDH373 have “bus
hold” on the data inputs, which retain the input’s last state
whenever the source driving the input goes to high impedance.
This eliminates the need for pullup/down resistors and pre-
vents floating inputs.
The CY74FCT163373 and the CY74FCT163LD373 are
designed with inputs and outputs capable of being driven by
5.0 V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power off disable feature enabling them to be used in
applications requiring live insertion.
Logic Block Diagrams CY74FCT163373, CY74FCT163H373,
CY74FCT163LD373, CY74FCT163LDH373
1
OE
Pin Configuration
SSOP/TSSOP
Top View
1
OE
1
O
1
1
O
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
LE
1
D
1
1
D
2
1
LE
1
D
1
D
1
O
1
GND
1
O
3
1
O
4
V
CC
1
O
5
1
O
6
GND
1
D
3
1
D
4
C
V
CC
1
D
5
1
D
6
GND
GND
1
D
7
1
D
8
2
D
1
2
D
2
TO 7 OTHER CHANNELS
1
O
7
1
O
8
2
OE
2
O
1
2
O
2
GND
2
LE
2
D
1
2
O
3
2
O
4
V
CC
2
O
5
2
O
6
GND
2
D
3
2
D
4
D
2
O
1
C
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
LE
TO 7 OTHER CHANNELS
Lite Drive is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
3901 North First Street
San Jose
• CA 95134 •
408-943-2600
March 19, 1997 - Revised April 20, 1998
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Pin Description
Name
D
LE
OE
O
Data Inputs
[1]
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
Three-State Outputs
[2]
Maximum Ratings
[3, 4]
Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature......................................
−55°C
to +125°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage Range ......................................0.5V to +4.6V
DC Input Voltage
................................................. −0.5V
to +7.0V
DC Output Voltage
.............................................. −0.5V
to +7.0V
Outputs
OE
L
L
L
H
O
H
L
Q
0
Z
DC Output Current
(Maximum Sink Current/Pin)
........................... −60
to +120 mA
Power Dissipation .......................................................... 1.0W
Function Table
D
H
L
X
X
Inputs
LE
H
H
L
X
Operating Range
Range
Industrial
Ambient
Temperature
−40°C
to +85°C
V
CC
2.7V to3.6V
Electrical Characteristics for Non Bus Hold Devices
Over the Operating Range V
CC
=2.7V to 3.6V
Parameter
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
I
CC
∆I
CC
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis
[6]
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
High Impedance Output Current
(Three-State Output pins)
High Impedance Output Current
(Three-State Output pins)
Short Circuit Current
[7]
Power-Off Disable
Quiescent Power Supply Current
Quiescent Power Supply Current
(TTL inputs HIGH)
V
CC
=Min., I
IN
=–18 mA
V
CC
=Max., V
I
=5.5
V
CC
=Max., V
I
=GND
V
CC
=Max., V
OUT
=5.5V
V
CC
=Max., V
OUT
=GND
V
CC
=Max., V
OUT
=GND
V
CC
=0V, V
OUT
≤4.5V
V
IN
≤0.2V,
V
IN
>V
CC
–0.2V
V
IN
=V
CC
–0.6V
[8]
V
CC
=Max.
V
CC
=Max.
0.1
2.0
–60
–135
100
–0.7
–1.2
±1
±1
±1
±1
–240
±100
10
30
Test Conditions
All Inputs
Min.
2.0
Typ.
[5]
Max.
5.5
0.8
Unit
V
V
mV
V
µA
µA
µA
µA
mA
µA
µA
µA
Note:
1. On the CY74FCT163H373 & CY74FCT163LDH373 these pins have “bus hold.
2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q
0
=Previous state of flip-flop.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
5. Typical values are at V
CC
=3.3V, T
A
= +25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
8. Per TTL driven input; all other inputs at V
CC
or GND.
2
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Electrical Characteristics For Bus Hold Devices
Over the Operating Range V
CC
=2.7V to 3.6V
Parameter
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
BBH
I
BBL
I
BHHO
I
BHLO
I
OZH
I
OZL
I
OS
I
OFF
I
CC
ICC
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis
[6]
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
Bus Hold Sustain Current on Bus Hold Input
[9]
V
CC
=Min.
V
I
=2.0V
V
I
=0.8V
Bus Hold Overdrive Current on Bus Hold Input
[9]
V
CC
=Max., V
I
=1.5V
High Impedance Output Current
(Three-State Output pins)
High Impedance Output Current
(Three-State Output pins)
Short Circuit Current
[7]
Power-Off Disable
Quiescent Power Supply Current
Quiescent Power supply Current
(TTL inputs HIGH)
V
CC
=Max., V
OUT
=V
CC
V
CC
=Max., V
OUT
=GND
V
CC
=Max., V
OUT
=GND
V
CC
=0V, V
OUT
≤4.5V
V
IN
≤0.2V,
V
IN
>V
CC
–0.2V
V
CC
=Max.
–60
–135
–50
+50
±500
±1
±1
–240
±100
+40
+350
V
CC
=Min., I
IN
=–18 mA
V
CC
=Max., V
I
=V
CC
100
–0.7
– 1.2
±100
±100
Test Conditions
All Inputs
Min.
2.0
Typ.
[5]
Max.
V
CC
0.8
Unit
V
V
mV
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
µA
µA
V
IN
=V
CC
–0.6V
[8]
V
CC
=Max.
Electrical Characteristics For Balanced Drive Devices
Over the Operating Range V
CC
=2.7V to 3.6V
Parameter
I
ODL
I
ODH
V
OH
Description
Output LOW Dynamic Current
[7]
Output HIGH Dynamic Current
[7]
Output HIGH Voltage
Test Conditions
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=Min., I
OH
= –0.1 mA
V
CC
=Min., I
OH
= –8 mA
V
CC
=3.0V, I
OH
= –24 mA
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
= 0.1mA
V
CC
=Min., I
OL
= 24 mA
0.3
Min.
45
–45
V
CC
–0.2
2.4
[10]
2.0
3.0
3.0
0.2
0.55
Typ.
[5]
Max.
180
–180
Unit
mA
mA
V
V
V
V
Electrical Characteristics For Lite Drive Devices
Over the Operating Range V
CC
=3.0V to 3.6V
Parameter
I
ODL
I
ODH
V
OH
V
OL
Description
Output LOW Dynamic Current
[7]
Test Conditions
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=3.0 V, I
OH
= –6 mA
V
CC
=3.0 V, I
OL
= 6 mA
Min.
15.0
–15.0
2.4
Typ.
[5]
Max.
45
–45
Unit
mA
mA
V
Output HIGH Dynamic Current
[7]
Output HIGH Voltage
Output LOW Voltage
3.0
0.55
V
Notes:
9. Pins with bus hold are described in Pin Description.
10. V
OH
=V
CC
–0.6 V at rated current.
3
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Capacitance
[6]
(T
A
= +25°C, f = 1.0 MHz)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
Test Conditions
Typ.
[5]
4.5
5.5
Max.
6.0
8.0
Unit
pF
pF
Power Supply Characteristics
Parameter
I
CCD
Description
Dynamic Power Supply
Current
[11]
Total Power Supply
Current
[12]
Test Conditions
V
CC
=Max., One Input Toggling, V
IN
=V
CC
or
50% Duty Cycle,
V
IN
=GND
Outputs Open, OE=GND
V
CC
=Max., f
1
=10 MHz, 50%
V
IN
=V
CC
or
Duty Cycle, Outputs Open, One V
IN
=GND
Bit Toggling, OE=GND
V
IN
=V
CC
–0.6V or
V
IN
=GND
V
CC
=Max., f
1
=2.5 MHz, 50%
V
IN
=V
CC
or
Duty Cycle, Outputs Open, Six- V
IN
=GND
teen Bits Toggling, OE=GND
V
IN
=V
CC
–0.6V or
V
IN
=GND
Typ.
[5]
50
Max.
75
Unit
µA/MHz
I
C
0.5
0.5
2.0
2.0
0.8
0.8
3.0
[13]
3.3
[13]
mA
mA
mA
mA
Switching Characteristics
Over the Operating Range
V
CC
=3.0V to 3.6V
[14,15]
CY74FCT163373A
CY74FCT163H373A
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SK(O)
Description
Propagation Delay D to Q
Output
Propagation Delay LE to Q
Output
Output Enable Time
Output Disable Time
Input Setup time
Input Hold time
Output Skew
[17]
Min.
1.5
2.0
1.5
1.5
2.0
1.5
Max.
4.8
8.0
6.2
5.6
-
-
0.5
CY74FCT163373C
CY74FCT163H373C
Min.
1.5
2.0
1.5
1.5
2.0
1.5
Max.
4.1
5.5
5.8
5.2
-
-
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[16]
1, 3
1, 5
1, 7, 8
1, 7, 8
1, 4
1, 4
Notes:
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
12. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f
0
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. For V
CC
=2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Switching Characteristics
Over the Operating Range
V
CC
=3.0V to 3.6V
[14,15]
CY74FCT163LD373
[18]
CY74FCT163LDH373
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SK(O)
Description
Propagation Delay Clock to
Q Output
Propagation Delay LE to Q
Output
Output Enable Time
Output Disable Time
Input Setup time
Input Hold time
Output Skew
[17]
2.0
1.5
Min.
Max.
8
13
12
7.5
-
-
0.5
1.5
1.5
2.0
1.5
0.5
CY74FCT163LD373A
[18]
CY74FCT163LDH373A
Min.
1.5
Max.
4.8
8.0
6.2
5.6
Unit
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[16]
1, 3
1. 3
1, 7, 8
1, 7, 8
1, 4
1, 4
Note:
18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF.
Ordering Information CY74FCT163373
Speed
(ns)
4.2
5.2
Ordering Code
CY74FCT163373CPAC
CY74FCT163373CPVC
CY74FCT163373APAC
CY74FCT163373APVC
Package
Name
Z48
O48
Z48
O48
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Operating
Range
Industrial
Ordering Information CY74FCT163H373
Speed
(ns)
4.2
5.2
Ordering Code
CY74FCT163H373CPAC
CY74FCT163H373CPVC
CY74FCT163H373APAC
CY74FCT163H373APVC
Package
Name
Z48
O48
Z48
O48
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Operating
Range
Industrial
Ordering Information CY74FCT163LD373
Speed
(ns)
5.2
8.0
Ordering Code
CY74FCT163LD373APAC
CY74FCT163LD373APVC
CY74FCT163LD373PAC
CY74FCT163LD373PVC
Package
Name
Z48
O48
Z48
O48
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Operating
Range
Industrial
5
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参数对比
与CY74FCT163LDH373PAC相近的元器件有:CY74FCT163LDH373APVC、CY74FCT163373CPVC。描述及对比如下:
型号 CY74FCT163LDH373PAC CY74FCT163LDH373APVC CY74FCT163373CPVC
描述 Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48 Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.025 INCH PITCH, SSOP-48 Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.025 INCH PITCH, SSOP-48
是否Rohs认证 不符合 不符合 不符合
零件包装代码 TSSOP SSOP SSOP
包装说明 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48 0.300 INCH, 0.025 INCH PITCH, SSOP-48 0.300 INCH, 0.025 INCH PITCH, SSOP-48
针数 48 48 48
Reach Compliance Code not_compliant not_compliant not_compliant
系列 FCT FCT FCT
JESD-30 代码 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48
JESD-609代码 e0 e0 e0
长度 12.5 mm 15.875 mm 15.875 mm
负载电容(CL) 30 pF 30 pF 50 pF
逻辑集成电路类型 BUS DRIVER BUS DRIVER BUS DRIVER
最大I(ol) 0.006 A 0.006 A 0.024 A
位数 8 8 8
功能数量 2 2 2
端口数量 2 2 2
端子数量 48 48 48
最高工作温度 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SSOP SSOP
封装等效代码 TSSOP48,.3,20 SSOP48,.4 SSOP48,.4
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
电源 3/3.3 V 3/3.3 V 3/3.3 V
Prop。Delay @ Nom-Sup 8 ns 4.8 ns 4.1 ns
传播延迟(tpd) 13 ns 8 ns 5.5 ns
认证状态 Not Qualified Not Qualified Not Qualified
座面最大高度 1.1 mm 2.794 mm 2.794 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V 2.7 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES
技术 CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING
端子节距 0.5 mm 0.635 mm 0.635 mm
端子位置 DUAL DUAL DUAL
宽度 6.1 mm 7.5 mm 7.5 mm
其他特性 BUS HOLD I/P'S BUS HOLD I/P\'S -
厂商名称 - Cypress(赛普拉斯) Cypress(赛普拉斯)
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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