首页 > 器件类别 > 逻辑 > 逻辑

CY74FCT16823BTPVC

Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56

器件类别:逻辑    逻辑   

厂商名称:Cypress(赛普拉斯)

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Cypress(赛普拉斯)
零件包装代码
SSOP
包装说明
SSOP, SSOP56,.4
针数
56
Reach Compliance Code
not_compliant
其他特性
WITH CLEAR AND CLOCK ENABLE
系列
FCT
JESD-30 代码
R-PDSO-G56
JESD-609代码
e0
长度
18.415 mm
负载电容(CL)
50 pF
逻辑集成电路类型
BUS DRIVER
最大I(ol)
0.064 A
位数
9
功能数量
2
端口数量
2
端子数量
56
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
SSOP
封装等效代码
SSOP56,.4
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
Prop。Delay @ Nom-Sup
7.5 ns
传播延迟(tpd)
15 ns
认证状态
Not Qualified
座面最大高度
2.794 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.635 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
触发器类型
POSITIVE EDGE
宽度
7.5 mm
文档预览
2823T
fax id: 7031
CY74FCT16823T
CY74FCT162823T
18-Bit Register
Features
• Low power, pin compatible replacement for ABT
functions
• FCT-E speed at 4.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of
−40°C
to +85°C
• V
CC
= 5V
±
10%
• Reduced system switching noise
• Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25°C
Functional Description
The CY74FCT16823T and the CY74FCT162823T 18-bit bus
interface register are designed for use in high-speed,
low-power systems needing wide registers and parity. 18-bit
operation is achieved by connecting the control lines of the two
9-bit registers. Flow-through pinout and small shrink packag-
ing aids in simplifying board layout. The outputs are designed
with a power-off disable feature to allow live insertion of
boards.
The CY74FCT16823T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162823T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162823T is ideal for driving transmission lines.
CY74FCT16823T Features:
• 64 mA sink current, 32 mA source current
• Typical V
OLP
(ground bounce) <1.0V at V
CC
= 5V,
T
A
= 25°C
CY74FCT162823T Features:
• Balanced 24 mA output drivers
Logic Block Diagrams
1
OE
Pin Configuration
SSOP/TSSOP
Top View
1
CLR
1
CLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
1
CLK
1
OE
1
Q
1
1
CLKEN
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
V
CC
R
C
D
1
D
1
1
Q
4
1
Q
1
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
GND
1
Q
7
1
Q
8
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
FCT16823-1
TO 8 OTHER CHANNELS
2
OE
1
Q
9
2
Q
1
2
Q
2
2
Q
3
2
CLR
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
2
CLK
2
CLKEN
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
R
C
D
2
D
2
GND
2
Q
1
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
TO 8 OTHER CHANNELS
FCT16823-2
FCT16823-3
Cypress Semiconductor Corporation
3901 North First Street
San Jose
• CA 95134 •
408-943-2600
August 1994 - Revised October 30, 1997
CY74FCT16823T
CY74FCT162823T
Pin Description
Name
D
CLK
CLKEN
CLR
OE
Q
Data Inputs
Clock Inputs
Clock Enable Inputs (Active LOW)
Asynchronous Clear Inputs (Active LOW)
Output Enable Inputs (Active LOW)
Three-State Outputs
Description
OE
H
L
L
H
H
L
L
CLR
X
L
H
H
H
H
H
Function Table
[1]
Inputs
CLKEN
X
X
H
L
L
L
L
CLK
X
X
X
D
X
X
X
L
H
L
H
Q
Z
L
Q
[2]
Outputs
Function
High Z
Clear
Hold
Load
Z
Z
L
H
Maximum Ratings
[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature
..................................... −55°C
to +125°C
Ambient Temperature with
Power Applied
.................................................. −55°C
to +125°C
DC Input Voltage
.................................................−0.5V
to +7.0V
DC Output Voltage
..............................................−0.5V
to +7.0V
DC Output Current
(Maximum Sink Current/Pin)
........................... −60
to +120 mA
Range
Industrial
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
−40°C
to +85°C
V
CC
5V
±
10%
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
Z = HIGH Impedance.
=LOW-to-HIGH transition.
2. Output level before indicated steady-state input conditions were established.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
2
CY74FCT16823T
CY74FCT162823T
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
O
I
OFF
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis
[6]
Test Conditions
Min.
2.0
Typ.
[5]
Max.
0.8
Unit
V
V
mV
V
µA
µA
µA
µA
mA
mA
µA
100
V
CC
=Min., I
IN
=−18 mA
V
CC
=Max., V
I
=V
CC
V
CC
=Max., V
I
=GND
V
CC
=Max., V
OUT
=2.7V
V
CC
=Max., V
OUT
=0.5V
V
CC
=Max., V
OUT
=GND
V
CC
=Max., V
OUT
=2.5V
V
CC
=0V, V
OUT
≤4.5V
[8]
−80
−50
−140
−0.7
−1.2
±1
±1
±1
±1
−200
−180
1
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
High Impedance Output Current
(Three-State Output pins)
High Impedance Output Current
(Three-State Output pins)
Short Circuit Current
[7]
Output Drive Current
[7]
Power-Off Disable
Output Drive Characteristics for CY74FCT16823T
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
V
CC
=Min., I
OH
=−3 mA
V
CC
=Min., I
OH
=−15 mA
V
CC
=Min., I
OH
=−32 mA
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
Min.
2.5
2.4
2.0
Typ.
[5]
3.5
3.5
3.0
0.2
0.55
V
Max.
Unit
V
Output Drive Characteristics for CY74FCT162823T
Parameter
I
ODL
I
ODH
V
OH
V
OL
Description
Output LOW Voltage
[7]
Test Conditions
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=Min., I
OH
=−24 mA
V
CC
=Min., I
OL
=24 mA
Min.
60
−60
2.4
Typ.
[5]
115
−115
3.3
0.3
Max.
150
−150
0.55
Unit
mA
mA
V
V
Output HIGH Voltage
[7]
Output HIGH Voltage
Output LOW Voltage
Capacitance
[9]
(T
A
= +25°C, f = 1.0 MHz)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
Test Conditions
Typ.
[5]
4.5
5.5
Max.
6.0
8.0
Unit
pF
pF
Notes:
5. Typical values are at V
CC
= 5.0V, T
A
= +25°C ambient.
6. This input is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
8. Tested at +25°C.
9. This parameter is guaranteed but not tested.
3
CY74FCT16823T
CY74FCT162823T
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Quiescent Power Supply
Current
Quiescent Power Supply
Current (TTL inputs HIGH)
Dynamic Power Supply
Current
[12]
V
CC
=Max.
V
CC
=Max.
V
CC
=Max.,
One Input Toggling,
50% Duty Cycle,
Outputs Open,
OE=CLKEN=GND
V
CC
=Max.,
f
0
=10 MHz,
50% Duty Cycle,
Outputs Open,
One Bit Toggling,
OE=CLKEN=GND
at f
1
=5 MHz
V
CC
=Max.,
at f
1
=2.5 MHz,
50% Duty Cycle,
Outputs Open,
Eighteen Bits Toggling,
OE=CLKEN=GND
f
0
=10 MHz
Test Conditions
[10]
V
IN
<0.2V
V
IN
>V
CC
−0.2V
V
IN
=3.4V
[11]
V
IN
=V
CC
or
V
IN
=GND
Min.
Typ.
[5]
5
0.5
75
Max.
500
1.5
120
Unit
µA
mA
µA/
MHz
I
C
Total Power Supply Current
[13]
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
0.8
1.3
1.7
3.2
mA
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
4.2
9.2
7.1
[14]
22.1
[14]
Notes:
10. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
11. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
13. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
4
CY74FCT16823T
CY74FCT162823T
Switching Characteristics
Over the Operating Range
[15]
CY74FCT16823AT
CY74FCT162823AT
Parameter
t
PLH
t
PHL
Description
Propagation Delay
CLK to Q
Condition
[16]
C
L
=50 pF
R
L
=500Ω
C
L
=300 pF
[17]
R
L
=500Ω
t
PHL
t
PZH
t
PZL
Propagation Delay
CLR to Q
Output Enable Time
OE to Q
C
L
=50 pF
R
L
=500Ω
C
L
=50 pF
R
L
=500Ω
C
L
=300 pF
[17]
R
L
=500Ω
t
PHZ
t
PLZ
Output Disable Time
OE to Q
C
L
=5 pF
[17]
R
L
=500Ω
C
L
=50 pF
R
L
=500Ω
t
SU
t
H
t
SU
t
H
t
W
t
W
t
REM
t
SK(O)
Set-Up Time
HIGH or LOW, D to CLK
Hold Time
HIGH or LOW, D to CLK
Set-Up Time
HIGH or LOW, CLKEN to CLK
Hold Time HIGH or LOW
CLKEN to CLK
CLK Pulse Width
HIGH or LOW
CLR Pulse Width LOW
Recovery Time
CLR to CLK
Output Skew
[18]
C
L
=50 pF
R
L
=500Ω
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
1.5
3.0
0.0
6.0
6.0
6.0
Max.
10.0
20.0
14.0
12.0
23.0
7.0
8.0
0.5
CY74FCT16823BT
CY74FCT162823BT
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3.0
1.5
3.0
0.0
6.0
6.0
6.0
Max.
7.5
15.0
9.0
8.0
15.0
6.5
7.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
4
4
9
9
5
5
6
ns
1, 7, 8
ns
ns
1, 5
1, 7, 8
Unit
ns
Fig.No.
[16]
1, 5
Switching Characteristics
Over the Operating Range
[15]
CY74FCT16823CT
CY74FCT16823ET
CY74FCT162823CT CY74FCT162823ET
Parameter
t
PLH
t
PHL
Description
Propagation Delay
CLK to Q
Condition
[16]
C
L
=50 pF
R
L
=500Ω
C
L
=300 pF
[17]
R
L
=500Ω
t
PHL
t
PZH
t
PZL
Propagation Delay
CLR to Q
Output Enable Time
OE to Q
C
L
=50 pF
R
L
=500Ω
C
L
=50 pF
R
L
=500Ω
C
L
=300 pF
[17]
R
L
=500Ω
t
PHZ
t
PLZ
Output Disable Time
OE to Q
C
L
=5 pF
[17]
R
L
=500Ω
C
L
=50 pF
R
L
=500Ω
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max.
6.0
12.5
6.1
5.5
12.5
5.2
6.5
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max.
4.4
8.0
4.4
4.4
9.0
3.6
3.6
ns
1, 7, 8
ns
ns
1, 5
1, 7, 8
Unit
ns
Fig.No.
[16]
1, 5
5
查看更多>
参数对比
与CY74FCT16823BTPVC相近的元器件有:CY74FCT16823CTPAC、CY74FCT16823ETPVC、CY74FCT162823ATPAC、CY74FCT16823ETPAC。描述及对比如下:
型号 CY74FCT16823BTPVC CY74FCT16823CTPAC CY74FCT16823ETPVC CY74FCT162823ATPAC CY74FCT16823ETPAC
描述 Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56 Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.300 INCH, 0.025 INCH PITCH, SSOP-56 Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 Bus Driver, FCT Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56
是否Rohs认证 不符合 不符合 不符合 不符合 不符合
零件包装代码 SSOP TSSOP SSOP TSSOP TSSOP
包装说明 SSOP, SSOP56,.4 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 0.300 INCH, 0.025 INCH PITCH, SSOP-56 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56
针数 56 56 56 56 56
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant not_compliant
其他特性 WITH CLEAR AND CLOCK ENABLE WITH CLEAR AND CLOCK ENABLE WITH CLEAR AND CLOCK ENABLE WITH CLEAR AND CLOCK ENABLE WITH CLEAR AND CLOCK ENABLE
系列 FCT FCT FCT FCT FCT
JESD-30 代码 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609代码 e0 e0 e0 e0 e0
长度 18.415 mm 14 mm 18.415 mm 14 mm 14 mm
负载电容(CL) 50 pF 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
最大I(ol) 0.064 A 0.064 A 0.064 A 0.024 A 0.064 A
位数 9 9 9 9 9
功能数量 2 2 2 2 2
端口数量 2 2 2 2 2
端子数量 56 56 56 56 56
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE WITH SERIES RESISTOR 3-STATE
输出极性 TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SSOP TSSOP SSOP TSSOP TSSOP
封装等效代码 SSOP56,.4 TSSOP56,.3,20 SSOP56,.4 TSSOP56,.3,20 TSSOP56,.3,20
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup 7.5 ns 6 ns 4.4 ns 10 ns 4.4 ns
传播延迟(tpd) 15 ns 12.5 ns 8 ns 20 ns 8 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.794 mm 1.1 mm 2.794 mm 1.1 mm 1.1 mm
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.635 mm 0.5 mm 0.635 mm 0.5 mm 0.5 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
宽度 7.5 mm 6.1 mm 7.5 mm 6.1 mm 6.1 mm
厂商名称 Cypress(赛普拉斯) Cypress(赛普拉斯) - Cypress(赛普拉斯) Cypress(赛普拉斯)
热门器件
热门资源推荐
器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
需要登录后才可以下载。
登录取消