RoboClock
®
CY7B9973V
High-Speed Multi-Output PLL Clock Buffer
Features
• 10-MHz – 200-MHz output operation
• Output-to-output skews < 350 ps
• 13 LVTTL 50% duty-cycle outputs capable of driving
50Ω terminated lines
• Phase-locked loop (PLL) LOCK indicator
• 3.3V LVTTL/LV differential (LVPECL) hot insertable
reference inputs
• Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6,
8, 10, 12, 16, 20)
• Operation with outputs operating at up to 10x input
frequency
• Low cycle-to-cycle jitter (<
±75
ps peak-peak)
• Single 3.3V ± 10% supply
• Pin-compatible with Motorola MPC973
• 52-pin TQFP package
Functional Description
The CY7B9973V Low-Voltage PLL Clock Buffer offers
user-selectable frequency control over system clock functions.
This twelve output clock driver provides the system integrator
selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs. An additional output is
dedicated to providing feedback information to allow the
internal PLL to multiply an external reference frequency by 4,
6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces
jitter and simplifies board layout.
The thirteen configurable outputs can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews at LVTTL levels.
The CY7B9973V has a flexible reference input scheme with
three different hot-insertion capable inputs. These inputs allow
the use of either differential LVPECL or single-ended LVTTL
inputs which can be dynamically selected to provide the
reference frequency.
Logic Diagram
PECL_CLK (11)
PECL_CLK (12)
PLL_En (6)
Ref_Sel (7)
TCLK_Sel (8)
1
LOCK (25)
Qa0 (50)
0
D Q
TCLK0 (9)
TCLK1 (10)
0
0
1
÷2/÷1
Qa1 (48)
Qa2 (46)
Qa3 (44)
Qb0 (38)
PHASE
DETECTOR
VCO
LPF
1
Ext_FB (31)
VCO_Sel (52)
D Q
Qb1 (36)
Qb2 (34)
fselFB2 (5)
MR/OE (2)
Reset
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
D Q
Qb3 (32)
Qc0 (23)
Qc1 (21)
fsela0:1 (43,42)
fselb0:1 (41,40)
fselc0:1 (20,19)
fselFB0:1 (27,26)
2
2
2
2
D Q
Qc2 (18)
Qc3 (16)
÷4, ÷6, ÷8, ÷10
Data Generator
0
÷2
1
D Q
QFB (29)
Inv_Clk (14)
Cypress Semiconductor Corporation
Document #: 38-07430 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised September 27, 2006
RoboClock
®
CY7B9973V
52-Lead Pinout (Top View)
fselFB0
26
25
24
23
22
Ext_FB
GNDO
GNDO
GNDO
VCCO
VCCO
VCCF
QFB
Qb0
Qb1
Qb2
Qb3
39 38 37 36 35 34 33 32 31 30 29 28 27
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
10 11 12 13
fselFB1
LOCK
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
CY7B9973V
21
20
19
18
17
16
15
14
PECL_CLK
PECL_CLK
MR/OE
FT1
FT2
TCLK0
fselFB2
PLL_En
Table 1. Divider Function Selects for Qa, Qb, Qc
fsela1
0
0
1
1
fsela0
0
1
0
1
Qa
fselb1
0
0
1
1
fselb0
0
1
0
1
Qb
fselc1
0
0
1
1
fselc0
0
1
0
1
Qc
÷
4
÷
6
÷
8
÷
12
fselFB0
0
1
0
1
0
1
0
1
TCLK_Sel
Ref_Sel
TCLK1
GNDA
÷
4
÷
6
÷
8
÷
10
Control Pin
VCO_Sel
Ref_Sel
TCLK_Sel
PLL_En
MR/OE
Inv_Clk
VCO/2
VCCA
÷
2
÷
4
÷
6
÷
8
Logic ‘1’
Table 2. Divider Function Select for QFB
fselFB2
0
0
0
0
1
1
1
1
fselFB1
0
0
1
1
0
0
1
1
QFB
Table 3. Control Pin Function Selects
Logic ‘0’
VCO
PECL
TCLK1
Enable PLL
Inverted Qc2, Qc3
Controlled by TCLK_Sel
TCLK0
Bypass PLL
Noninverted Qc2, Qc3
÷
4
÷
6
÷
8
÷
10
÷
8
÷
12
÷
16
÷
20
Master Reset/Output Hi-Z Enable Outputs
Document #: 38-07430 Rev. *B
Page 2 of 8
RoboClock
®
CY7B9973V
Pin Definitions
Name
Q[a:c][0:3]
QFB
Ext_FB
Ref_Sel
Pin #
50,48,46,44
38,36,34,32
23,21,18,16
29
31
7
Type
LVTTL
Output
Description
Clock Output.
These outputs provide numerous divide functions determined by the
fsel[a:c][0:1] and the fselFB[0:2] inputs. See
Table 1
and
Table 2
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LV-Diff.
PECL
Input
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
LVTTL
Input
[1]
Power
Power
Power
Ground
PLL Feedback Input.
This input is used to connect one of the Clock Outputs (usually
QFB) to the feedback input of the PLL.
Reference Select Input.
The Ref_Sel input controls the reference input to the PLL. When
LOW the input is selected by the TCLK_Sel input. When HIGH the PECL_CLK is selected.
This input has an internal pull-up.
TTL Clock Select Input.
The TCLK_Sel input controls which TCLK[0,1] input will be used
as the reference input if Ref_Sel is LOW. When TCLK_Sel is LOW TCLK0 is selected.
When TCLK_Sel is HIGH TCLK1 is selected. This input has an internal pull-up.
LVTTL Reference Inputs.
These inputs provide the Reference frequency for the internal
PLL when selected by Ref_Sel and TCLK_Sel.
Differential Reference Inputs.
This LV-Differential PECL input provides the Reference
frequency for the internal PLL when selected by Ref_Sel.
Output Divider Function Select.
Each pair controls the divider function of the respective
bank of outputs. See
Table 1.
Feedback Output Divider Function Select.
These inputs control the divider function of
the Feedback output QFB. See
Table 2.
VCO Frequency Select Input.
This input selects the nominal operating range of the VCO
used in the PLL. When VCO_Sel is HIGH the VCO range is 200-480 MHz. When VCO_Sel
is LOW the VCO range is 100-240 MHz.
PLL Bypass Select.
When this input is HIGH the internal Phase Locked Loop (PLL)
provides the internal clocks to operate the part. When this input is LOW the internal PLL
is bypassed and the selected reference input provides the clocks to operate the part.
PLL Bypass Mode Control Inputs.
When PLL_En is HIGH these inputs are ignored and
may be set to any logic level or left open. These inputs have an internal pull-up.
Invert Mode.
This input only affects the Qc bank. When this input is HIGH, Qc2 and Qc3
are inverted from the “normal” phase of Qc0 and Qc1. When this input is LOW all outputs
of the Qc bank are in the “normal” phase alignment.
Master Reset (active LOW) and Output Enable (active HIGH) Input.
Note: when
MR/OE is deasserted (set to HIGH) the PLL will have been disturbed and the outputs will
be at an indeterminate frequency until it is relocked.
PLL Power.
Feedback Buffer Power.
Output Buffer Power.
PLL Ground.
Output Buffer Ground.
PLL Lock Indicator.
When HIGH this output indicates that the internal PLL is locked to
the reference signal. When LOW the PLL is attempting to acquire lock. Note: If there is
no activity on the selected reference input LOCK may not accurately reflect the state of
the internal PLL. This pin will drive logic, but not Thevenin terminated transmission lines.
It is always active and does not go to a high impedance state. This output provides TEST
MODE information when PLL_En is LOW.
TCLK_Sel
8
TCLK0
TCLK1
9, 10
PECL_CLK 11,12
PECL_CLK
fsel[a:c][0:1] 43, 42, 41,
40, 20,19
fselFB[0:1]
fselFB2
VCO_Sel
27,26 5
52
PLL_En
6
FT1, FT2
Inv_Clk
3, 4
14
MR/OE
2
VCCA
VCCF
VCCO
GNDA
GNDO
LOCK
13
28
17, 22, 33,
37,45,49
1
15, 24, 30,
Ground
35, 39, 47, 51
25
LVTTL
Output
Note:
1. Includes internal PULL-UP. If this pin is left unconnected it will assume a HIGH level.
Document #: 38-07430 Rev. *B
Page 3 of 8
RoboClock
®
CY7B9973V
Block Diagram Description
(see figure, page 1)
Phase Frequency Detector and Filter
These two blocks accept signals from the reference inputs
(TCLK0, TCLK1 or PECL_CLK) and the FB input (Ext_FB).
Correction information is then generated to control the
frequency of the Voltage Controlled Oscillator (VCO). These
two blocks, along with the VCO, form a (PLL) that tracks the
incoming reference signal.
The Robo973 has a flexible reference input scheme. These
inputs allow the use of either differential LVPECL or one of two
single-ended LVTTL inputs. The reference inputs are tolerant
to hot insertion and can be changed dynamically.
VCO, Control Logic, and Divider
The VCO accepts analog control inputs from the PLL filter
block. The VCO_Sel control pin setting determines the
nominal operational frequency range of the VCO (f
NOM
). When
VCO_Sel is HIGH the VCO operating range is 200–480 MHz.
For systems that need lower frequencies, VCO_Sel can be set
LOW, which changes the VCO operating range to
100–240 MHz.
Data Generator
The Data Generator is comprised of four independent banks:
three banks for clock outputs and one bank for feedback. Each
clock output bank has four low-skew, high-fanout output
buffers (Q[a:c][0:3]), controlled by two divide function select
inputs (fsel[a:c][0:1]).
The feedback bank has one high-fanout output buffer (QFB).
This output is usually connected to the selected feedback input
(Ext_FB). This feedback output has three divider function
selects fselFB[0:2].
Inv_Clk Pin Function
The Qc bank has signal invert capability. The four outputs of
the Qc bank will act as two pairs of complementary outputs
when the Inv_Clk pin is driven HIGH. In complementary output
mode, Qc0 and Qc1 are noninverting (i.e., in phase with the
other banks), Qc2 and Qc3 are inverting outputs (i.e., inverted
from the other banks). When the Inv_Clk pin is driven LOW,
the outputs will not invert. Inversion of the outputs are
independent of the divide functions. Therefore, clock outputs
of Qc bank can be inverted and divided at the same time.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. An unacceptable phase error is declared when the
phase difference between the two inputs is greater than about
700 ps.
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH,
a Watchdog circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time-out period is based upon a divided down reference
clock.
This assumes that there is activity on the selected reference
input. If there is no activity on the selected reference input then
the LOCK detect pin may not accurately reflect the state of the
internal PLL.
The LOCK pin has been designed with an intentionally
reduced output drive capability to minimize noise and power
dissipation. This pin will drive logic, but not Thevenin-termi-
nated transmission lines. It is also unaffected by the MR/OE
input and is always active.
PLL Bypass Mode Description
The device will enter PLL bypass mode when the PLL_En is
driven LOW. In factory PLL bypass mode, the device will
operate with its internal PLL disconnected; input signals
supplied to the reference input will be used in place of the PLL
output. In PLL bypass mode the Ext_FB input is ignored. All
functions of the device are still operational in PLL bypass
mode.
Factory Test Reset
When in PLL bypass mode (PLL_En = LOW), the device can
be reset to a deterministic state by driving the MR/OE input
LOW. When the MR/OE input is driven LOW in PLL bypass
mode, all clock outputs will go to HI-Z; after the selected
reference clock pin has 5 positive transitions, all the internal
finite state machines (FSM) will be set to a deterministic state.
The deterministic state of the state machines will depend on
the configurations of the divide selects and frequency select
input. All clock outputs will stay in high-impedance mode and
all FSMs will stay in the deterministic state until MR/OE is
deasserted. When MR/OE is deasserted (with PLL_En still at
LOW), the device will reenter PLL bypass mode.
Safe Operating Zone
The device will operate below its maximum allowable junction
temperature (t
J
< 150°C) in any configuration of multiply or
divide with all outputs loaded to the data sheet maximum (i.e.,
with 25-pF load and 0-m/s air flow).
Document #: 38-07430 Rev. *B
Page 4 of 8
RoboClock
®
CY7B9973V
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –40°C to +150°C
Ambient Temperature with Power Applied .. –40°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Input Voltage....................................–0.3V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 2000V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... ±200 mA
Operating Range
Range
Commercial
Ambient Temperature
0°C to +70°C
V
CC
3.3V
±10%
DC CHARACTERISTICS
Over the Operating Range
Parameter
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
Description
Input HIGH Voltage
Input LOW Voltage
Peak-to-Peak Input Voltage PECL_CLK
Common Mode Range (Crossing) PECL_CLK
Output HIGH Voltage All “Q” Outputs
Output HIGH Voltage LOCK Output
Output LOW Voltage “Q” Output
Output LOW Voltage LOCK Output
Input Current
[4]
Note 2
I
OH
= –20 mA
[3]
I
OH
= –2
mA
[3]
I
OL
= +20 mA
I
OL
= +2 mA
All control inputs
GND < V
IN
< V
CC
PECL_CLK and
TCLK[0:1] GND <
V
IN
< V
CC
I
I
Hot Insertion Input Current
PECL_CLK and
TCLK[0:1] V
IN
<
3.63V V
CC
= GND
Sum all V
CC
pins
PLL_En=LOW
reference off
Outputs unloaded
fselFB = 010 (
÷
8)
ref = 50 MHz
Note 5
Test Conditions
Min.
2.0
–
400
0.8
2.4
2.4
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
Max.
V
CC
+ 0.3
0.8
V
cc
V
cc
–
–
0.5
0.5
+150
+500
Unit
V
V
mV
V
V
V
V
V
uA
uA
–
–
100
uA
I
CCQ
Maximum Quiescent Supply Current
–
50
150
mA
I
CCD
Maximum Dynamic Supply Current (Neglecting
Output Load Current)
Input Capacitance
–
320
400
mA
C
IN
–
–
4
pF
PLL INPUT REFERENCE CHARACTERISTICS
Over the Operating Range
Parameter
t
r,
t
f
f
ref
t
refDC
Description
TCLK Input Rise/Fall Time
Reference Input Frequency
Reference Input Duty Cycle
Test Conditions
Note 5
Min.
–
14
25
Max.
3.0
120
75
Unit
ns
MHz
%
Notes:
2. V
CMR
is the measured at the point that both inputs achieve the same voltage.
3. The CY7B9973V clock outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
4. Inputs have pull-up resistors which affect input current.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-07430 Rev. *B
Page 5 of 8
