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CY7C024/024A/0241

CY7C025/0251

4K x 16/18 and 8K x 16/18 Dual-Port

Static RAM with SEM, INT, BUSY

Features

■

Functional Description

The CY7C024/024A/0241 and CY7C025/0251 are low power

CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various

arbitration schemes are included on the CY7C024/ 0241 and

CY7C025/0251 to handle situations when multiple processors

access the same piece of data. Two ports are provided,

permitting independent, asynchronous access for reads and

writes to any location in memory. The CY7C024/ 0241 and

CY7C025/0251 can be used as standalone 16 or 18-bit dual-port

static RAMs or multiple devices can be combined to function as

a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S

pin is provided for implementing 32-/36-bit or wider memory

applications without the need for separate master and slave

devices or additional discrete logic. Application areas include

interprocessor/multiprocessor designs, communications status

buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE), Read

or Write Enable (R/W), and Output Enable (OE). Two flags are

provided on each port (BUSY and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The Interrupt Flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a chip select (CE) pin.

The CY7C024/024A/0241 and CY7C025/0251 are available in

84-pin Pb-free PLCCs, 84-pin PLCCs (CY7C024 and CY7C025

only), 100-pin Pb-free Thin Quad Plastic Flatplack (TQFP), and

100-pin Thin Quad Plastic Flatpack.

True dual-ported memory cells, which allow simultaneous

reads of the same memory location

4K x 16 organization (CY7C024/024A

[1]

)

4K x 18 organization (CY7C0241)

8K x 16 organization (CY7C025)

8K x 18 organization (CY7C0251)

0.65 micron CMOS for optimum speed and power

High speed access: 15 ns

Low operating power: I

= 150 mA (typ)

Fully asynchronous operation

Automatic power down

Expandable data bus to 32/36 bits or more using Master/Slave

chip select when using more than one device

On-chip arbitration logic

Semaphores included to permit software handshaking

between ports

INT flag for port-to-port communication

Separate upper-byte and lower-byte control

Pin select for Master or Slave

Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin

(Pb-free) TQFP, and 100-pin TQFP

Note

1. CY7C024 and CY7C024A are functionally identical.

Cypress Semiconductor Corporation

Document #: 38-06035 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised December 09, 2008

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CY7C024/024A/0241

CY7C025/0251

Logic Block Diagram

R/W

[4]

I/O

– I/O

15L

[3]

I/O

– I/O

I/O

CONTROL

I/O

CONTROL

I/O

– I/O

15R

[4]

I/O

– I/O

[3]

[2]

BUSY

12R

(CY7C025/0251)

BUSY

(CY7C025/0251)

[2]

12L

11L

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

DECODER

11R

R/W

SEM

INT

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

M/S

INT

Pin Configurations

Figure 1. 84-Pin PLCC (Top View)

SEM

GND

I/O

[5]

11L

R/W

I/O

10L

INT

BUSY

GND

M/S

BUSY

INT

11 10 9 8 7 6 5 4 3 2

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

GND

I/O

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

SEM

[6]

11R

GND

I/O

15R

R/W

I/O

13R

I/O

14R

I/O

10R

I/O

11R

I/O

12R

GND

10R

1 84 83 82 81 80 79 78 77 76 75

CY7C024/024A/025

Notes

2. BUSY is an output in master mode and an input in slave mode.

3. I/O

–I/O

on the CY7C0241/0251.

4. I/O

–I/O

on the CY7C0241/0251.

5. A

12L

on the CY7C025/0251.

6. A

12R

on the CY7C025/0251.

Document #: 38-06035 Rev. *D

Page 2 of 21

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CY7C024/024A/0241

CY7C025/0251

Pin Configurations

(continued)

Figure 2. 100-Pin TQFP (Top View)

R/W

SEM

[5]

11L

10L

I/O

GND

I/O

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

GND

I/O

INT

BUSY

GND

M/S

BUSY

INT

CY7C024/5

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GND

I/O

15R

I/O

10R

I/O

11R

I/O

12R

R/W

GND

SEM

[6]

11R

10R

Pin Definitions

Left Port

R/W

–A

11/12L

I/O

–I/O

15/17L

SEM

INT

BUSY

M/S

GND

Right Port

R/W

–A

11/12R

I/O

–I/O

15/17R

SEM

INT

BUSY

Chip Enable

Read/Write Enable

Output Enable

Address

Data Bus Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Interrupt Flag

Busy Flag

Master or Slave Select

Power

Ground

Description

Document #: 38-06035 Rev. *D

I/O

13R

I/O

14R

Page 3 of 21

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CY7C024/024A/0241

CY7C025/0251

Selection Guide

Parameter

Maximum Access Time (ns)

Typical Operating Current (mA)

Typical Standby Current for I

SB1

(mA)

7C024/024A/0241–15

7C025/0251–15

190

7C024/0241–25

7C025/0251–25

170

7C024/0241–35

7C025/0251–35

160

7C024/0241–55

7C025/0251–55

150

Architecture

The CY7C024/024A/0241 and CY7C025/0251 consist of an

array of 4K words of 16/18 bits each and 8K words of 16/18 bits

each of dual-port RAM cells, I/O and address lines, and control

signals (CE, OE, R/W). These control pins permit independent

access for reads or writes to any location in memory. To handle

simultaneous writes/reads to the same location, a BUSY pin is

provided on each port. Two interrupt (INT) pins can be used for

port-to-port communication. Two semaphore (SEM) control pins

are used for allocating shared resources. With the M/S pin, the

CY7C024/024A/0241 and CY7C025/0251 can function as a

master (BUSY pins are outputs) or as a slave (BUSY pins are

inputs). The CY7C024/024A/0241 and CY7C025/0251 have an

automatic power down feature controlled by CE. Each port is

provided with its own output enable control (OE), which allows

data to be read from the device.

Each port can read the other port’s mailbox without resetting the

interrupt. The active state of the BUSY signal (to a port) prevents

the port from setting the interrupt to the winning port. Also, an

active BUSY to a port prevents that port from reading its own

mailbox and thus resetting the interrupt to it.

If your application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin.

The operation of the interrupts and their interaction with Busy are

summarized in

Table 2

on page 5.

Busy

The CY7C024/024A/0241 and CY7C025/0251 provide on-chip

arbitration to resolve simultaneous memory location access

(contention). If both ports’ CEs are asserted and an address

match occurs within t

of each other, the busy logic determines

which port has access. If t

is violated, one port definitely gains

permission to the location, but which one is not predictable.

BUSY is asserted t

BLA

after an address match or t

BLC

after CE

is taken LOW.

Functional Description

Write Operation

Data must be set up for a duration of t

before the rising edge

of R/W to guarantee a valid write. A write operation is controlled

by either the R/W pin (see

Figure 7)

or the CE pin (see

Figure 8).

Required inputs for non contention operations are summarized

Table 1.

If a location is being written to by one port and the opposite port

attempts to read that location, a port-to-port flowthrough delay

must occur before the data is read on the output; otherwise the

data read is not deterministic. Data is valid on the port t

DDD

after

the data is presented on the other port.

Master/Slave

A M/S pin is provided to expand the word width by configuring

the device as either a master or a slave. The BUSY output of the

master is connected to the BUSY input of the slave. This allows

the device to interface to a master device with no external

components. Writing to slave devices must be delayed until after

the BUSY input has settled (t

BLC

or t

BLA

). Otherwise, the slave

chip may begin a write cycle during a contention situation. When

tied HIGH, the M/S pin allows the device to be used as a master

and, therefore, the BUSY line is an output. BUSY can then be

used to send the arbitration outcome to a slave.

Read Operation

When reading the device, the user must assert both the OE and

CE pins. Data is available t

ACE

after CE or t

DOE

after OE is

asserted. If the user of the CY7C024/024A/0241 or

CY7C025/0251 wishes to access a semaphore flag, then the

SEM pin must be asserted instead of the CE pin, and OE must

also be asserted.

Semaphore Operation

The CY7C024/024A/0241 and CY7C025/0251 provide eight

semaphore latches, which are separate from the dual-port

memory locations. Semaphores are used to reserve resources

that are shared between the two ports. The state of the

semaphore indicates that a resource is in use. For example, if

the left port wants to request a given resource, it sets a latch by

writing a zero to a semaphore location. The left port then verifies

its success in setting the latch by reading it. After writing to the

semaphore, SEM or OE must be deasserted for tSOP before

attempting to read the semaphore. The semaphore value is

available t

SWRD

+ t

DOE

after the rising edge of the semaphore

write. If the left port was successful (reads a zero), it assumes

control of the shared resource, otherwise (reads a one) it

assumes the right port has control and continues to poll the

semaphore. When the right side has relinquished control of the

semaphore (by writing a one), the left side succeeds in gaining

control of the semaphore. If the left side no longer requires the

semaphore, a one is written to cancel its request.

Page 4 of 21

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (FFF for the

CY7C024/024A/0241, 1FFF for the CY7C025/0251) is the

mailbox for the right port and the second-highest memory

location (FFE for the CY7C024/024A/0241, 1FFE for the

CY7C025/0251) is the mailbox for the left port. When one port

writes to the other port’s mailbox, an interrupt is generated to the

owner. The interrupt is reset when the owner reads the contents

of the mailbox. The message is user defined.

Document #: 38-06035 Rev. *D

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CY7C024/024A/0241

CY7C025/0251

Semaphores are accessed by asserting SEM LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A0–2 represents the

semaphore address. OE and R/W are used in the same manner

as a normal memory access. When writing or reading a

semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O

is used. If a zero is

written to the left port of an available semaphore, a one appears

at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing zero

(the left port in this case). If the left port now relinquishes control

by writing a one to the semaphore, the semaphore is set to one

Table 1. Non-Contending Read/Write

Inputs

R/W

SEM

High Z

Data In

High Z

Data Out

High Z

Data Out

Data In

for both sides. However, if the right port had requested the

semaphore (written a zero) while the left port had control, the

right port immediately owns the semaphore as soon as the left

port released it.

Table 3

shows sample semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines

output the semaphore value. The read value is latched in an

output register to prevent the semaphore from changing state

during a write from the other port. If both ports attempt to access

the semaphore within t

SPS

of each other, the semaphore is

definitely obtained by one side or the other, but there is no

guarantee which side controls the semaphore

Outputs

I/O

–I/O

7[3]

I/O

–I/O

15[4]

High Z

Data In

High Z

Data In

Data Out

High Z

Data Out

High Z

Data Out

Data In

Operation

Deselected: Power Down

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

Outputs Disabled

Read Data in Semaphore Flag

Write D

IN0

into Semaphore Flag

Write D

IN0

into Semaphore Flag

Not Allowed

Table 2. Interrupt Operation Example (Assumes BUSY

=BUSY

=HIGH)

[7]

Function

Set Right INT

Flag

Reset Right INT

Flag

Set Left INT

Flag

Reset Left INT

Flag

Left Port

R/W

0L–11L

(1)FFF

(1)FFE

INT

[8]

[9]

R/W

Right Port

0R–11R

(1)FFF

(1)FFE

INT

[9]

[8]

Document #: 38-06035 Rev. *D

Page 5 of 21

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