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CY7C1019CV33
128K x 8 Static RAM
Features
• Pin and function compatible with CY7C1019BV33
• High speed
— t
AA
= 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 48-ball VFBGA, 32-pin TSOP II and 400-mil
SOJ package
• Also available in lead-free 48-ball VFBGA and 32-pin
TSOP II packages
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in Standard 48-ball FBGA,
32-pin TSOP II and 400-mil-wide SOJ packages.
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
Logic Block Diagram
Pin Configuration
SOJ/TSOP II
Top View
A
0
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
I/O
INPUT BUFFER
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
ROW DECODER
1
I/O
SENSE AMPS
2
512 x 256 x 8
ARRAY
I/O
I/O
I/O
I/O
I/O
3
4
5
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
6
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 9, 2006
CY7C1019CV33
Pin Configuration
(continued)
48-ball FBGA
(Top View)
1
NC
I/O
0
I/O
1
V
SS
V
CC
I/O
2
I/O
3
NC
2
OE
NC
NC
NC
NC
NC
NC
A
10
3
A
2
A
1
A
0
NC
NC
A
14
A
15
A
16
4
A
6
A
5
A
4
A
3
NC
A
11
A
12
A
13
5
A
7
CE
NC
NC
NC
I/O
4
WE
A
9
6
NC
I/O
7
I/O
6
V
CC
V
SS
I/O
5
A
8
NC
A
B
C
D
E
F
G
H
Selection Guide
7C1019CV33-8
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
8
85
5
7C1019CV33-10
10
80
5
7C1019CV33-12
12
75
5
7C1019CV33-15
15
70
5
Unit
ns
mA
mA
Document #: 38-05130 Rev. *E
Page 2 of 10
CY7C1019CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
... –0.5V to + 4.6V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
10%
3.3V
±
10%
Electrical Characteristics
Over the Operating Range
7C1019CV33
-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS[2.]
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[1]
Input Load
Current
GND < V
I
< V
CC
Test Conditions Min.
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.0
–0.3
–1
–1
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
85
2.0
–0.3
–1
–1
Max.
7C1019CV33
-10
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
80
2.0
–0.3
–1
–1
Max.
7C1019CV33
-12
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
75
2.0
–0.3
–1
–1
Max.
7C1019CV33
-15
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
70
Max.
Unit
V
V
V
V
µA
µA
mA
mA
Output Leakage GND < V
I
< V
CC
,
Current
Output Disabled
Output Short
Circuit Current
V
CC
Operating
Supply Current
Automatic CE
Power-down
Current
—TTL Inputs
Automatic CE
Power-down
Current
—CMOS Inputs
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE >
V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
I
SB1
15
15
15
15
mA
I
SB2
5
5
5
5
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *E
Page 3 of 10
CY7C1019CV33
AC Test Loads and Waveforms
[4]
8-ns devices:
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Z = 50
Ω
10-, 12-, 15-ns devices:
3.3V
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
(a)
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
(b)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
R2
351Ω
Rise Time: 1 V/ns
(c)
[5]
Fall Time: 1 V/ns
(d)
Switching Characteristics
Over the Operating Range
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU[8]
t
PD[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High
Z
[6, 7]
0
8
8
7
7
0
0
6
5
0
3
4
10
8
8
0
0
7
5
0
3
5
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
3
4
0
10
12
9
9
0
0
8
6
0
3
6
0
4
3
5
0
12
15
10
10
0
0
10
8
0
3
7
3
8
5
0
5
3
6
0
15
8
8
3
10
5
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
[9, 10]
Notes:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05130 Rev. *E
Page 4 of 10
