written into the location specified on the address pins (A
0
through A
17
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location specified
on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15
. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041 is available in a standard 44-pin 400-mil-wide
body width SOJ and 44-pin TSOP II package with center pow-
er and ground (revolutionary) pinout.
Functional Description
The CY7C1041 is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
Logic Block Diagram
INPUT BUFFER
Pin Configuration
SOJ
TSOP II
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
256K x 16
ARRAY
1024 x 4096
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1041–1
A
17
A
16
A
15
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
14
A
13
A
12
A
11
A
10
1041–2
ROW DECODER
Selection Guide
7C1041-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current Com’l
(mA)
Com’l
Ind’l
Shaded areas contain advance information.
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
SENSE AMPS
7C1041-15
15
260
3
0.5
6
7C1041-17
17
250
3
0.5
6
7C1041-20
20
230
3
0.5
6
7C1041-25
25
220
3
0.5
6
12
280
3
L
0.5
6
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 23, 1998
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
CY7C1041
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
0.5
Electrical Characteristics
Over the Operating Range
7C1041-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l
Com’l
Ind’l
L
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
0.4
2.2
–0.5
–1
–1
V
CC
+ 0.5
0.8
+1
+1
280
40
2.2
–0.5
–1
–1
Max.
7C1041-15
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
260
40
2.2
–0.5
–1
–1
Max.
7C1041-17
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
250
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
3
0.5
6
3
0.5
6
3
0.5
6
mA
mA
mA
Shaded areas contain advance information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
2
PRELIMINARY
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l
Com’l
Ind’l
L
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–1
–1
7C1041-20
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
230
40
2.2
–0.5
–1
–1
Max.
CY7C1041
7C1041-25
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
220
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
3
0.5
6
3
0.5
6
mA
mA
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤
3ns
R1 481
Ω
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
≤
3 ns
1041–3
1041–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
3
PRELIMINARY
Switching Characteristics
[4]
Over the Operating Range
7C1041-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CY7C1041
7C1041-15
Min.
15
Max.
7C1041-17
Min.
17
Max.
Unit
ns
17
3
17
7
0
7
3
7
0
17
7
0
7
17
14
14
0
0
14
8
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
12
ns
ns
Description
Min.
12
Max.
12
3
12
6
0
6
3
6
0
12
6
0
6
12
10
10
0
0
10
7
0
3
6
10
12
15
12
12
0
0
12
8
0
3
0
0
3
0
3
15
15
7
7
7
15
7
7
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte Enable to End of Write
WRITE CYCLE
[7,8]
7
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
