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CY7C1069AV33
2M x 8 Static RAM
Features
■
Functional Description
The CY7C1069AV33 is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits. Writing to the device is
accomplished by enabling the chip (by taking CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) as well as forcing the Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. See
“Truth
Table”
on page 8 for a complete description of Read and Write
modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH or
CE
2
LOW), the outputs are disabled (OE HIGH), or during a
Write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout and a
60-ball fine-pitch ball grid array (FBGA) package.
High Speed
❐
t
AA
= 10, 12 ns
Low Active Power
❐
990 mW (max.)
Operating Voltages of 3.3 ± 0.3V
2.0V Data Retention
Automatic Power Down when deselected
TTL-compatible Inputs and Outputs
Easy Memory Expansion with CE
1
and CE
2
features
Available in Pb-free and non Pb-free 54-pin TSOP II, non
Pb-free 60-ball Fine-Pitch Ball Grid Array (FBGA) package
■
■
■
■
■
■
■
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
CE
1
CE
2
WE
OE
Data in Drivers
I/O
0
I/O
1
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
2048K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
17
A
18
A
19
A
20
A
16
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2009
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CY7C1069AV33
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–10
10
275
50
–12
12
260
50
Unit
ns
mA
mA
Pin Configuration
Figure 1. 54-Pin TSOP II
[1, 2]
Top View
NC
V
CC
NC
I/O
6
V
SS
I/O
7
A
4
A
3
A
2
A
1
A
0
NC
CE
1
V
CC
WE
CE
2
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
NC
V
SS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
V
SS
NC
I/O
5
V
CC
I/O
4
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
DNU
A
20
A
10
A
11
A
12
A
13
A
14
I/O
3
V
SS
I/O
2
NC
V
CC
NC
Notes
1. NC pins are not connected on the die.
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
Document #: 38-05255 Rev. *G
Page 2
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CY7C1069AV33
Pin Configuration
Figure 2. 54-Pin TSOP II
[1, 2]
1
2
(Top View)
3
4
5
6
NC
NC
NC
NC
NC
NC
NC
NC
I/O0
V
SS
OE
NC
NC
I/O1
A0
A3
A5
A
17
A18
A14
A
12
A9
A1
A4
A6
A
7
A
16
A15
A13
A10
A2
CE1
NC
CE2
NC
I/O4
A
B
C
D
E
F
G
H
I/O5 V
CC
I/O6 V
SS
NC
WE
I/O
7
NC
V
CC I/O2
I/O3
NC
NC DNU
A19
A8
A11 A20
NC
NC
NC
NC
NC
NC
Document #: 38-05255 Rev. *G
Page 3
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CY7C1069AV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V
CC
to Relative
GND
[3]
.....–0.5V
to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
.................................... –0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power Down Current
—TTL Inputs
Automatic CE
Power Down Current
—CMOS Inputs
GND < V
I
< V
CC
V
CC
= Max.,
f = f
MAX
= 1/t
RC
CE
2
< V
IL
,
Max. V
CC
, CE
1
> V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
CE
2
< 0.3V, Max. V
CC
,
CE
1
> V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
–10
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
275
70
2.0
–0.3
–1
–1
Max
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
260
70
–12
Max
Unit
V
V
V
V
μA
μA
mA
mA
50
50
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
Notes
3. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05255 Rev. *G
Page 4
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