• Available in Pb-free and non Pb-free 54-pin TSOP II
package
Functional Description
The CY7C1069BV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
LOW) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE LOW) as well as forcing the Output Enable (OE) LOW
while forcing the Write Enable (WE) HIGH. See the truth table
at the back of this data sheet for a complete description of
Read and Write modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW and WE LOW).
The CY7C1069BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
INPUT BUFFER
Pin Configurations
[1, 2]
54-pin TSOP II (Top View)
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
2M x 8
ARRAY
I/O
0
–I/O
7
COLUMN
DECODER
WE
OE
CE
NC
V
CC
NC
I/O
6
V
SS
I/O
7
A
4
A
3
A
2
A
1
A
0
NC
CE
V
CC
WE
DNU/V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
V
SS
NC
I/O
5
V
CC
I/O
4
A
5
A
6
A
7
A
8
A
9
NC
OE
V
SS
A
20
A
10
A
11
A
12
A
13
A
14
I/O
3
V
SS
I/O
2
NC
DNU/V
SS
ROW DECODER
SENSE AMPS
A
19
A
18
A
17
A
16
A
15
I/O
0
V
CC
I/O
1
NC
V
SS
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
V
CC
NC
Notes:
1. DNU/V
CC
Pin (#16) has to be left floating or connected to V
CC
and DNU/V
SS
Pin (#40) has to be left floating or connected to V
SS
to ensure proper application.
2. NC - No Connect Pins are not connected to the die.
Cypress Semiconductor Corporation
Document #: 38-05694 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY7C1069BV33
Selection Guide
–10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
Industrial
Commercial/Industrial
10
275
275
50
–12
12
260
260
50
mA
Unit
ns
mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW
Voltage
[3]
GND < V
I
< V
CC
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Comm’l/
Ind’l
Comm’l
Ind’l
Input Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
275
275
70
2.0
–0.3
–1
–1
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
260
260
70
–12
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled
I
SB2
50
50
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
6
8
Unit
pF
pF
Thermal Resistance
[4]
Parameter
Description
Test Conditions
TSOP-II
49.95
3.34
Unit
°C/W
°C/W
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
Thermal Resistance (Junction to Case)
thermal impedance, per EIA/JESD51.
Notes:
3. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05694 Rev. *B
Page 2 of 7
CY7C1069BV33
AC Test Loads and Waveforms
[5]
50Ω
OUTPUT
Z0 = 50Ω
(a)
V
TH
= 1.5V
30 pF* *Capacitive Load consists of all
components of the test environment
All input pulses
3.3V
GND
Rise time > 1V/ns
90%
10%
(c)
[6]
R1 317
Ω
3.3V
OUTPUT
*Including
jig and
scope
90%
10%
Fall time: > 1V/ns
5 pF*
R2
351Ω
(b)
AC Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Cycle
[10, 11]
Write Cycle Time
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
V
CC
(typical) to the First Access
[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8]
CE LOW to Low-Z
[8]
CE to High-Z
[8]
CE to Power-up
[9]
CE to Power-down
[9]
Description
–10
Min.
1
10
10
3
10
5
1
5
3
5
0
10
10
7
7
0
0
7
5.5
0
3
5
12
8
8
0
0
8
6
0
3
0
3
1
3
Max.
Min.
1
12
–12
Max.
Unit
ms
ns
12
12
6
6
6
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
ns
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
7. t
POWER
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. t
HZOE
, t
HZSCE
, t
HZWE
and t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±200
mV
from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of
CE LOW
and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05694 Rev. *B
Page 3 of 7
CY7C1069BV33
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[13, 14]
ADDRESS
t
RC
CE
t
ASCE
OE
t
DOE
t
LZOE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZSCE
t
PU
50%
DATA VALID
t
PD
50%
I
SB
I
CC
t
HZOE
t
HZSCE
HIGH
IMPEDANCE
Notes:
12. Device is continuously selected. CE = V
IL
.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
