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CY7C1318CV18, CY7C1320CV18

18-Mbit DDR II SRAM 2-Word

Burst Architecture

18-Mbit DDR II SRAM 2-Word Burst Architecture

Features

■

Configurations

CY7C1318CV18 – 1M × 18

CY7C1320CV18 – 512K × 36

18-Mbit density (1 M × 18, 512 K × 36)

267-MHz clock for high bandwidth

2-word burst for reducing address bus frequency

Double data rate (DDR) interfaces

(data transferred at 534 MHz) at 267 MHz

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

Echo clocks (CQ and CQ) simplify data capture in high speed

systems

Synchronous internally self-timed writes

DDR II operates with 1.5 cycle read latency when delay lock

loop (DLL) is enabled

Operates similar to a DDR I device with one cycle read latency

in DLL Off mode

1.8 V core power supply with high-speed transceiver logic

(HSTL) inputs and outputs

Variable drive HSTL output buffers

Expanded HSTL output voltage (1.4 V – V

)

Available in 165-ball fine pitch ball grid array (FPBGA) package

(13 × 15 × 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

DLL for accurate data placement

Functional Description

The CY7C1318CV18, and CY7C1320CV18 are 1.8 V

synchronous pipelined SRAMs equipped with DDR II

architecture. The DDR II consists of an SRAM core with

advanced synchronous peripheral circuitry and a one-bit burst

counter. Addresses for read and write are latched on alternate

rising edges of the input (K) clock. Write data is registered on the

rising edges of both K and K. Read data is driven on the rising

edges of C and C if provided, or on the rising edge of K and K if

C/C are not provided. For CY7C1318CV18 and

CY7C1320CV18, the burst counter takes in the least significant

bit of the external address and bursts two 18-bit words (in the

case of CY7C1318CV18) of two 36-bit words (in the case of

CY7C1320CV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■

Cypress Semiconductor Corporation

Document Number: 001-07160 Rev. *I

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 27, 2010

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CY7C1318CV18, CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

Burst

Logic

(19:0)

Write Add. Decode

Read Add. Decode

(19:1)

Address

Write

Reg

512K x 18 Array

Write

Reg

512K x 18 Array

CLK

Gen.

Output

Logic

Control

R/W

DOFF

Read Data Reg.

Control

Logic

REF

R/W

BWS

[1:0]

Reg.

Reg. 18

[17:0]

Logic Block Diagram (CY7C1320CV18)

Burst

Logic

(18:0)

Write Add. Decode

Read Add. Decode

(18:1)

Address

Write

Reg

256K x 36 Array

Write

Reg

256K x 36 Array

CLK

Gen.

Output

Logic

Control

R/W

DOFF

Read Data Reg.

Control

Logic

REF

R/W

BWS

[3:0]

Reg.

Reg. 36

[35:0]

Document Number: 001-07160 Rev. *I

Page 2 of 29

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CY7C1318CV18, CY7C1320CV18

Contents

Selection Guide ................................................................ 4

Pin Configuration ............................................................. 5

165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 5

Pin Definitions .................................................................. 6

Functional Overview ........................................................ 8

Read Operations ......................................................... 8

Write Operations ......................................................... 8

Byte Write Operations ................................................. 8

Single Clock Mode ...................................................... 8

DDR Operation ............................................................ 8

Depth Expansion ......................................................... 8

Programmable Impedance .......................................... 9

Echo Clocks ................................................................ 9

DLL .............................................................................. 9

Application Example ........................................................ 9

Truth Table ...................................................................... 10

Burst Address Table ...................................................... 10

Write Cycle Descriptions ............................................... 10

Write Cycle Descriptions ............................................... 11

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12

Disabling the JTAG Feature ...................................... 12

Test Access Port—Test Clock ................................... 12

Test Mode Select (TMS) ........................................... 12

Test Data-In (TDI) ..................................................... 12

Test Data-Out (TDO) ................................................. 12

Performing a TAP Reset ........................................... 12

TAP Registers ........................................................... 12

TAP Instruction Set ................................................... 12

TAP Controller State Diagram ....................................... 14

TAP Controller Block Diagram ...................................... 15

TAP Electrical Characteristics ...................................... 15

TAP AC Switching Characteristics ............................... 16

TAP Timing and Test Conditions .................................. 16

Identification Register Definitions ................................ 17

Scan Register Sizes ....................................................... 17

Instruction Codes ........................................................... 17

Boundary Scan Order .................................................... 18

Power Up Sequence in DDR II SRAM ........................... 19

Power Up Sequence ................................................. 19

DLL Constraints ......................................................... 19

Maximum Ratings ........................................................... 20

Operating Range ............................................................. 20

Neutron Soft Error Immunity ......................................... 20

Electrical Characteristics ............................................... 20

DC Electrical Characteristics ..................................... 20

AC Electrical Characteristics ..................................... 21

Capacitance .................................................................... 21

Thermal Resistance ........................................................ 21

Switching Characteristics .............................................. 22

Switching Waveforms .................................................... 24

Ordering Information ...................................................... 25

Ordering Code Definition ........................................... 25

Package Diagram ............................................................ 26

Acronyms ........................................................................ 27

Document Conventions ................................................. 27

Units of Measure ....................................................... 27

Document History Page ................................................. 28

Sales, Solutions, and Legal Information ...................... 29

Worldwide Sales and Design Support ....................... 29

Products .................................................................... 29

PSoC Solutions ......................................................... 29

Document Number: 001-07160 Rev. *I

Page 3 of 29

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CY7C1318CV18, CY7C1320CV18

Selection Guide

Description

Maximum operating frequency

Maximum operating current

×18

×36

267 MHz

267

805

855

250 MHz

250

730

775

200 MHz

200

600

635

167 MHz

167

510

540

Unit

MHz

Document Number: 001-07160 Rev. *I

Page 4 of 29

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参数对比

与CY7C1318CV18-200BZXC相近的元器件有：CY7C1318CV18-167BZC、CY7C1318CV18-250BZI、CY7C1318CV18-200BZI、CY7C1318CV18-250BZC、CY7C1318CV18-250BZXC、CY7C1320CV18-267BZXC、CY7C1320CV18-167BZC、CY7C1320CV18-250BZC、CY7C1320CV18-250BZXC。描述及对比如下：

型号	CY7C1318CV18-200BZXC	CY7C1318CV18-167BZC	CY7C1318CV18-250BZI	CY7C1318CV18-200BZI	CY7C1318CV18-250BZC	CY7C1318CV18-250BZXC	CY7C1320CV18-267BZXC	CY7C1320CV18-167BZC	CY7C1320CV18-250BZC	CY7C1320CV18-250BZXC
描述	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	1MX18 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	512KX36 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	512KX36 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数	165	165	165	165	165	165	165	165	165	165
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
最长访问时间	0.45 ns	0.5 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.45 ns	0.5 ns	0.45 ns	0.45 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
长度	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
内存密度	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit
内存集成电路类型	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
内存宽度	18	18	18	18	18	18	36	36	36	36
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	165	165	165	165	165	165	165	165	165	165
字数	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	524288 words	524288 words	524288 words	524288 words
字数代码	1000000	1000000	1000000	1000000	1000000	1000000	512000	512000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	1MX18	1MX18	1MX18	1MX18	1MX18	1MX18	512KX36	512KX36	512KX36	512KX36
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
座面最大高度	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	TIN SILVER COPPER	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN SILVER COPPER	NOT SPECIFIED	TIN LEAD	TIN LEAD	TIN SILVER COPPER
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm
是否无铅	不含铅	含铅	含铅	含铅	含铅	不含铅	-	含铅	含铅	不含铅
是否Rohs认证	符合	不符合	不符合	不符合	不符合	符合	-	不符合	不符合	符合
厂商名称	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	-	-	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
JESD-609代码	e1	e0	e0	e0	e0	e1	-	e0	e0	e1
湿度敏感等级	NOT SPECIFIED	3	3	3	3	3	-	3	3	3
峰值回流温度（摄氏度）	260	220	220	220	NOT SPECIFIED	260	-	220	220	260
处于峰值回流温度下的最长时间	20	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	40	-	NOT SPECIFIED	NOT SPECIFIED	20
Base Number Matches	1	1	1	1	1	1	-	-	-	-