CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
18-Mbit DDR-II SRAM 4-Word
Burst Architecture
Features
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Functional Description
The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and
CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with four 8-bit words in the case of CY7C1317CV18
and four 9-bit words in the case of CY7C1917CV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘00’ internally in the case of CY7C1317CV18 and
CY7C1917CV18. For CY7C1319CV18 and CY7C1321CV18,
the burst counter takes in the least two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319CV18, and four 36-bit words in the case of
CY7C1321CV18, sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
300 MHz clock for high bandwidth
4-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
DDR-II operates with 1.5 cycle read latency when the DLL is
enabled
Operates similar to a DDR-I device with 1 cycle read latency in
DLL off mode
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
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Configurations
CY7C1317CV18 – 2M x 8
CY7C1917CV18 – 2M x 9
CY7C1319CV18 – 1M x 18
CY7C1321CV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
300 MHz
300
770
770
810
890
278 MHz
278
720
720
760
830
250 MHz
250
670
670
700
765
200 MHz
200
580
580
600
655
167 MHz
167
515
515
540
600
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-07161 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 18, 2008
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CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Logic Block Diagram (CY7C1317CV18)
A
(18:0)
LD
K
K
DOFF
19
Write Add. Decode
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Address
Register
8
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
8
CQ
CQ
8
DQ
[7:0]
Read Data Reg.
32
16
Control
Logic
16
Reg.
Reg.
Reg.
V
REF
R/W
NWS
[1:0]
8
8
8
Logic Block Diagram (CY7C1917CV18)
A
(18:0)
LD
K
K
DOFF
19
Write Add. Decode
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Address
Register
9
512K x 9 Array
512K x 9 Array
512K x 9 Array
512K x 9 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
9
CQ
CQ
9
DQ
[8:0]
Read Data Reg.
36
18
Control
Logic
18
Reg.
Reg.
Reg.
V
REF
R/W
BWS
[0]
9
9
9
Document Number: 001-07161 Rev. *D
Page 2 of 31
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CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Logic Block Diagram (CY7C1319CV18)
A
(1:0)
2
A
(19:0)
20
LD
K
K
DOFF
18
Burst
Logic
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Write Add. Decode
Read Add. Decode
A
(19:2)
Address
Register
256K x 18 Array
256K x 18 Array
256K x 18 Array
256K x 18 Array
18
CLK
Gen.
Output
Logic
Control
R/W
C
C
18
CQ
CQ
18
DQ
[17:0]
Read Data Reg.
72
36
Control
Logic
36
Reg.
Reg.
Reg.
V
REF
R/W
BWS
[1:0]
18
18
18
Logic Block Diagram (CY7C1321CV18)
A
(1:0)
2
A
(18:0)
19
LD
K
K
DOFF
17
Burst
Logic
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Write Add. Decode
Read Add. Decode
A
(18:2)
Address
Register
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
36
CLK
Gen.
Output
Logic
Control
R/W
C
C
36
CQ
CQ
36
DQ
[35:0]
Read Data Reg.
144
72
Control
Logic
72
Reg.
Reg.
Reg.
V
REF
R/W
BWS
[3:0]
36
36
36
Document Number: 001-07161 Rev. *D
Page 3 of 31
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CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Pin Configuration
The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1317CV18 (2M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
CY7C1917CV18 (2M x 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-07161 Rev. *D
Page 4 of 31
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CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Pin Configuration
(continued)
The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1319CV18 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1321CV18 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
NC/144M NC/36M
Document Number: 001-07161 Rev. *D
Page 5 of 31
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