ment is controlled by the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
1
MODE
(A
0
,A
1
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
15
17
17
15
128K X 18
MEMORY
ARRAY
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
Q
DQ[7:0]
BYTEWRITE
REGISTERS
D
BW
0
CE
1
CE
2
CE
3
D
ENABLE Q
CE REGISTER
CLK
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ
[15:0]
DP
[1:0]
Pin
Selection Guide
7C1324–117
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
7.5
350
1.0
7C1324–100
8.0
325
1.0
7C1324–80
8.5
300
1.0
7C1324–50
11.0
250
1.0
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 4, 1999
CY7C1324
Pin Configuration
100-Lead TQFP
OE
ADSC
BWS
1
BWS
0
ADSP
ADV
84
83
BWE
V
DD
CE
1
CE
2
CE
3
CLK
V
SS
GW
NC
NC
A6
A7
A
8
82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
NC
V
DD
NC
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
100
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
A
10
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
NC
V
DD
ZZ
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE0
CY7C1324
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
NC
BYTE1
MODE
A
5
A
4
A
3
A
2
A
1
A
0
DNU
DNU
A
11
A
12
V
SS
DNU
DNU
2
V
DD
A
15
A
16
A
13
A
14
CY7C1324
Functional Description
(continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BWS
[1:0]
) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS
0
controls DQ
[7:0]
and DP
0
while
BWS
1
controls DQ
[15:8]
and DP
1
. All I/Os are three-stated dur-
ing a byte write. Since these are common I/O devices, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
DQ
[15:0]
and DP
[1:0]
. As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWS
[1:0]
)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register,
burst counter/control logic and delivered to the RAM core. The
information presented to DQ
[15:0]
and DP
[1:0]
will be written
into the specified address location. Byte writes are allowed,
with BWS
0
controlling DQ
[7:0]
and DP
0
while BWS
1
controlling
DQ
[15:8]
and DP
1
. All I/Os are three-stated when a write is
detected, even a byte write. Since these are common I/O de-
vices, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ
[15:0]
and DP
[1:0]
. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regard-
less of the state of OE.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the Address Register, burst counter
/control logic and presented to the memory core. If the OE
input is asserted LOW, the requested data will be available at
the data outputs a maximum to t
CDV
after clock rise. ADSP is
ignored if CE
1
is HIGH.
Burst Sequences
This family of devices provide a 2-bit wrap around burst
counter inside the SRAM. The burst counter is fed by A
[1:0]
,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address
A
X + 1
, A
x
00
01
10
11
Second
Address
A
X + 1
, A
x
01
00
11
10
Third
Address
A
X + 1
, A
x
10
11
00
01
Fourth
Address
A
X + 1
, A
x
11
10
01
00
Table 2. Counter Implementation for a Linear Sequence
First
Address
A
X + 1
, A
x
00
01
10
11
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting a HIGH
input on ZZ places the SRAM in a power conservation “sleep”
mode. Two clock cycles are required to enter into or exit from
this “sleep” mode. While in this mode, data integrity is guaran-
teed. Accesses pending when entering the “sleep” mode are
not considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must re-
main inactive for the duration of t
ZZREC
after the ZZ input re-
turns low
Second
Address
A
X + 1
, A
x
01
10
11
00
Third
Address
A
X + 1
, A
x
10
11
00
01
Fourth
Address
A
X + 1
, A
x
11
00
01
10
3
CY7C1324
Cycle Description Table
[1, 2, 3]
Cycle Description
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
SNOOZE MODE, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADD
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
1
H
L
L
L
X
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE
3
X
X
H
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSP
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
HIGH-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS
[1:0].
Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
4
CY7C1324
Pin Descriptions
TQFP Pin
Number
85
Name
ADSC
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
1
is deasserted HIGH.
A
1
, A
0
Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
[1:0]
to select one of the 128K address
locations. Sampled at the rising edge of the CLK, if CE
1
, CE
2
, and CE
3
are sampled
active, and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BWS
0
controls DQ
[7:0]
and DP
0
, BWS
1
controls DQ
[15:8]
and DP
1
. See Write Cycle Descriptions table for further details.
Advance Input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used
to conduct a global write, independent of the state of BWE and BWS
[1:0]
. Global writes
override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
2
and CE
3
, to select/deselect the device. CE
1
gates ADSP.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power
standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults
to interleaved burst order.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
[1:0]
are placed in a three-state condition. The outputs are automatically
three-stated when a WRITE cycle is detected.
Bidirectional Data Parity lines. These behave identical to DQ
[15:0]
described above.
These signals can be used as parity bits for bytes 0 and 1 respectively.
Power supply inputs to the core of the device. Should be connected to 3.3V power
stm32/stm8
