CY7C1325F
4-Mb (256K x 18) Flow-Through Sync SRAM
Features
• 256K X 18 common I/O
• 3.3V –5% and +10% core power supply (V
DD
)
• 2.5V or 3.3V I/O supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
— 11.0ns (66-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
• “ZZ” Sleep Mode option
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1325F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1325F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Functional Description
[1]
The CY7C1325F is a 262,144 x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
Logic Block Diagram
A0,A1,A
MODE
ADDRESS
REGISTER
A[1:0]
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B
,DQP
B
WRITE REGISTER
DQ
B
,DQP
B
WRITE DRIVER
BW
B
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
BW
A
BWE
GW
DQ
A
,DQP
A
WRITE REGISTER
DQ
A
,DQP
A
WRITE DRIVER
INPUT
REGISTERS
DQs
DQP
A
DQP
B
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
ZZ
SLEEP
CONTROL
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05215 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 13, 2004
CY7C1325F
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
133 MHz
6.5
225
40
117 MHz
7.5
220
40
100 MHz
8.0
205
40
66 MHz
11.0
195
40
Unit
ns
mA
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
BW
B
BW
A
CE
3
CE
1
CE
2
NC
NC
V
DD
V
SS
CLK
OE
ADSC
ADSP
ADV
A
86
85
84
83
82
GW
BWE
A
A
99
98
97
96
95
94
93
92
91
90
89
88
87
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
C
DQ
C
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
BYTE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
100
81
A
CY7C1325F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
38
39
40
41
V
DD
42
MODE
A
V
SS
NC
NC
A
A
NC
NC
A
1
A
0
A
A
A
43
A
A
A
A
Document #: 38-05215 Rev. *B
A
Page 2 of 17
CY7C1325F
Pin Configurations
(continued)
119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
NC
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
NC
DQ
A
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Pin Descriptions
Name
A0, A1, A
TQFP
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,80,81,
82,99,100
93,94
88
BGA
P4,A4,A2,
A3,A5,A6,
B3,B5,C2,
C3,C5,C6,
R2,R6,T2,
T3,T5,T6
L5,G3
H4
I/O
Description
Input-
Address Inputs used to select one of the 256K address locations.
Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
BW
A,
BW
B
GW
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct
Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the
Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW
[A:B]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a byte write.
Input-Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
BWE
CLK
87
89
M4
K4
CE
1
CE
2
CE
3
98
E4
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE
2
and CE
3
to select/deselect the device.
ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE and CE to select/deselect the device.
1
2
97
92
B2
B6
Document #: 38-05215 Rev. *B
Page 3 of 17
CY7C1325F
Pin Descriptions
(continued)
Name
OE
TQFP
86
BGA
F4
I/O
Description
Input-
Output Enable, asynchronous input, active LOW.
Controls the
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK.
When
Synchronous asserted, it automatically increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of
Synchronous
CLK, active LOW.
When asserted LOW, addresses presented to the
device are captured in the address registers. A
[1:0]
are also loaded into
the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE
1
is deasserted HIGH
Input-
Address Strobe from Controller, sampled on the rising edge of
Synchronous
CLK, active LOW.
When asserted LOW, addresses presented to the
device are captured in the address registers. A
[1:0]
are also loaded into
the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
Input-
ZZ “sleep” Input, active HIGH.
When asserted HIGH places the de-
Asynchronous vice in a non-time-critical “sleep” condition with data integrity preserved.
For normal operation, this pin has to be LOW or left floating. ZZ pin has
an internal pull-down.
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data
Synchronous register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQP
[A:B]
are placed
in a three-state condition.
Power
Supply
Ground
Power supply inputs to the core of the device.
Ground for the core of the device.
ADV
ADSP
83
84
G4
A4
ADSC
85
B4
ZZ
64
T7
DQs
DQP
A,
DQP
B
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
15,41,65,
91
5,10,17,21
,26,40,55,
60,67,71,
76,90
E7,F6,G7,
H6,K7,L6,
N6,P7,D1,
E2,G2,H1,
K2,L1,M2,
N1,D6,P2
C4,J2,J4,
J6,R4
D3,E3,F3,
H3,K3,L3,
M3,N3,P3,
B5,E5,F5,
G5,H5,K5,
M5,N5,P5
V
DD
V
SS
V
DDQ
4,11,20, A1,F1,J1,
27,54,61, M1,U1,A7,
70,77
F7,J7,M7,
U7
31
R3
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order.
When tied to GND selects linear burst sequence.
When tied to V
DD
or left floating selects interleaved burst sequence.
This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
No Connects.
Not Internally connected to the die.
NC
1,2,3,6,7, B1,C1,E1,
14,16,25, G1,K1,P1,
28,29,30, R1,T1,D2,
38,39,42, F2,H2,L2,
43,51,52, N2,U2,J3,
53,56,57, U3,D4,L4,
66,75,78, T4,U4,J5,
79,95,96 U5,E6,G6,
K6,M6,P6,
U6,B7,C7,
D7,H7,L7,
N7,R7,R5
Document #: 38-05215 Rev. *B
Page 4 of 17
CY7C1325F
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
C0
) is 6.5 ns (133-MHz device).
The CY7C1325F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium
®
and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:B]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
CDV
after clock
rise. ADSP is ignored if CE
1
is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, CE
3
are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW
[A:B]
)are ignored during this first
clock cycle. If the write inputs are asserted active ( see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise,the appropriate data will be latched
and written into the device.Byte writes are allowed. During
byte writes, BW
A
controls DQ
A
and BW
B
controls DQ
B
.All I/Os
are three-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
[A:B]
)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
[A:D]
will be
written into the specified address location. Byte writes are
allowed. During byte writes, BW
A
controls DQ
A
, BW
B
controls
DQ
B
. All I/Os are three-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
DQs. As a safety precaution, the data lines are three-stated
once a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1325F provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A
[1:0]
, and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
.
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A
1
, A
0
00
01
10
11
Second
Address
A
1
, A
0
01
10
11
00
Third
Address
A
1
, A
0
10
11
00
01
Fourth
Address
A
1
, A
0
11
00
01
10
Document #: 38-05215 Rev. *B
Page 5 of 17
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